Ex Parte YAMAZAKI et al

Patent Trials and Appeals Board

May 13, 2019

12906565 - (D) (P.T.A.B. May. 13, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/906,565 10/18/2010
31780 7590 05/15/2019
Robinson Intellectual Property Law Office, P.C.
3975 Fair Ridge Drive
Suite 20 North
Fairfax, VA 22033
FIRST NAMED INVENTOR
Shunpei YAMAZAKI
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
0756-9011 1325
EXAMINER
MAI,ANHD
ART UNIT PAPER NUMBER
2829
NOTIFICATION DATE DELIVERY MODE
05/15/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ptomail@riplo.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SHUNPEI YAMAZAKI, JUN KOY AMA, and KEITARO IMAI
Appeal2017-007418
Application 12/906,565 1
Technology Center 2800
Before ROBERT E. NAPPI, ERIC S. FRAHM, and MICHAEL T. CYGAN,
Administrative Patent Judges.
CYGAN, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF CASE
Introduction
Appellants appeal under 35 U.S.C. § 134(a) from the Examiner's
Final Rejection of claims 1, 3, 7-10, 12, 15, 19-22, 24, 27, 32-38, 40-45,
and 47-58. We have jurisdiction under 35 U.S.C. § 6(b). An oral hearing
was conducted on April 15, 2019. 2
1 According to Appellants, the real party in interest is Semiconductor Energy
Laboratory Co., Ltd. App. Br. 4.
2 Appellants were represented at oral hearing by Stephen P. Catlin, USPTO
Registration No. 36,101. Mr. Catlin also presented oral arguments for
Appeal2017-007418
Application 12/906,565
We affirm.
Disclosed Subject Matter and Exemplary Claim
The disclosed subject matter relates to semiconductor devices; in
particular, to providing a device structure that prevents damage from high
flow-through current and reduces leakage current. Spec. ,r,r 8-9. For that
purpose, the disclosed subject matter employs, for example, a stack of a
transistor using an oxide semiconductor and a transistor using a material
other than an oxide semiconductor.
Independent claim 1 is exemplary of the disclosed invention, and
reads as follows:
1. A semiconductor device comprising:
a single crystal silicon substrate;
a first transistor comprising a channel formation region in
the single crystal silicon substrate, impurity regions formed in
the single crystal silicon substrate with the channel formation
region interposed therebetween, a first gate insulating layer
over the channel formation region, a first gate electrode over
the first gate insulating layer, and a first source electrode and a
first drain electrode which are electrically connected to the
impurity regions;
a first insulating layer over the first gate electrode;
a second-insulating layer over the first insulating layer;
embedded conductive layers embedded in the second
insulating layer, the embedded conductive layers and the
second insulating layer having a same thickness, and bottom
surfaces of the embedded conductive layers coinciding with a
bottom surface of the second insulating layer;
a third insulating layer over the second insulating layer
and the embedded conductive layers;
a second transistor comprising one of the embedded
conductive layers as a second gate electrode, the second gate
related Appeal No. 2017-007360 (U.S. Application No. 14/187,830), which
contains similar subject matter.
2
Appeal2017-007418
Application 12/906,565
electrode being over the first insulating layer, the third
insulating layer as a second gate insulating layer over the
second gate electrode, an oxide semiconductor layer over the
second gate insulating layer, and a second source electrode and
a second drain electrode electrically connected to the oxide
semiconductor layer;
a fourth insulating layer over the third insulating layer,
the oxide semiconductor layer, the second source electrode, and
the second drain electrode; and
a conductive layer over the fourth insulating layer,
wherein the first gate electrode is electrically connected
to the oxide semiconductor layer through a serial connection
comprising one of the embedded conductive layers, the
conductive layer, and one of the second source electrode and
the second drain electrode.
Independent claims 12, 24, 27, 32, 38, and 45 recite limitations
of similar scope as the limitations recited in claim 1. Dependent
claims 3, 7-10, 15, 19-22, 33-37, 40-44, and 47-58 each incorporate
the limitations of the independent claims from which they depend.
Examiner's Rejection
The Examiner rejects claims 1, 7-10, 12, 19-22, 24, 38, 40-45, and
47-51 under 35 U.S.C. § I03(a) as being obvious over the combination of
Cederbaum et al. (US 5,112,765, issued May 12, 1992) (hereinafter
"Cederbaum") and Iwasaki (US 2009/0045397 Al, published Feb. 19,
2009). Final Act. 3.
The Examiner rejects claims 3, 15, 27, 32-37, and 52-58 under 35
U.S.C. § I03(a) as being obvious over the combination of Cederbaum and
3
Appeal2017-007418
Application 12/906,565
Iwasaki, further in view of Yamazaki et al. (US 2009/0078939 Al,
published March 26, 2009). Final Act. 13, 17.
ANALYSIS
We have reviewed the Examiner's rejection (Final Act. 2-25) in light
of Appellants' contentions that the Examiner has erred (App. Br. 13-22;
Reply Br. 1-9). Further, we have reviewed the Examiner's response to
Appellants' contentions (Ans. 2-10). We are not persuaded by Appellants'
arguments of error in the Examiner's rejection.
Claims 1, 7-10, 12, 19-22, 24, 38, 40-45, and 47-51
With respect to the rejection of claims 1, 7-10, 12, 19-22, 24, 38, 40-
45, and 47-51 under 35 U.S.C. § I03(a), the issue raised by Appellants is
whether the combination of the relied-upon teachings or suggestions of
Cederbaum with the relied-upon teachings or suggestions of Iwasaki would
have made obvious the claimed invention. App. Br. 14--20.
The Examiner finds that one of ordinary skill in the art would have
combined the teachings or suggestions of Cederbaum and Iwasaki as set
forth in the rejections under 35 U.S.C. § I03(a) for the following reasons.
First, that this would "form a TFT [thin film transistor] having a large
ON/OFF ratio." Final Act. 5. Second, that it would be within the general
skill of a worker in the art to select a known material on the basis of its
suitability for the intended use as a matter of obvious design choice. Id.
(citing In re Leshin, 277 F.2d 197 (CCPA 1960)). Third, that Iwasaki
teaches or suggests that prior art polycrystalline silicon TFT requires high
temperature processing, and that Iwasaki' s oxide semiconductor TFT can be
formed at a low temperature with a simpler process, having similar or better
4
Appeal2017-007418
Application 12/906,565
characteristics than that of a comparable polycrystalline silicon based
transistor. Id. at 26.
Appellants contend that the combinations would not have been
obvious, for the following reasons. First, that the Examiner has not
presented a prima facie case ofunpatentability. App. Br. 14. Second, that
the Examiner has not provided any evidence that the ON/OFF ratio of
Iwasaki would be large relative to Cederbaum's existing device. Id. Third,
that oxide semiconductors are naturally N-type TFTs, and would be
incompatible for substitution for Cederbaum's P-type TFTs, and that the
oxide semiconductor taught by Iwasaki has inferior properties to the
polysilicon taught by Cederbaum, for example, having inferior speed. Id.
We do not find Appellants' contentions persuasive.
With respect to Appellants' first contention, that the Examiner has not
set forth a prima facie case of obviousness, the
[US]PTO carries its procedural burden of establishing a prima
facie case when its rejection satisfies 35 U.S.C. § 132, in
"notify[ing] the applicant ... [by] stating the reasons for [its]
rejection, or objection or requirement, together with such
information and references as may be useful in judging of the
propriety of continuing the prosecution of [the] application."
In re Jung, 637 F.3d 1356, 1362 (Fed. Cir. 2011) (quoting 35 U.S.C. § 132)
(alterations in original). The USPTO violates 35 U.S.C. § 132 "when a
rejection is so uninformative that it prevents the applicant from recognizing
and seeking to counter the grounds for rejection." Chester v. Miller,
906 F.2d 1574, 1578 (Fed. Cir. 1990). But if the USPTO "adequately
explain[ s] the shortcomings it perceives ... the burden shifts to the applicant
5
Appeal2017-007418
Application 12/906,565
to rebut the prima facie case with evidence and/or argument." Hyatt v.
Dudas, 492 F.3d at 1370 (Fed. Cir. 2007).
Here, the Examiner relies upon Iwasaki' s teaching or suggestion of an
oxide semiconductor layer that forms a TFT with a large ON/OFF ratio.
Final Act. 5. This teaching or suggestion is set forth by Iwasaki as a
property of its disclosed TFT having an amorphous oxide channel layer.
Iwasaki Abstract. Iwasaki states that the ON/OFF ratio in its device may be
"more than 106." Iwasaki ,r,r 152, 164. In this manner, the Examiner has
provided detailed explanation of the features from each reference and the
manner by which one having ordinary skill in the art would combine those
teachings or suggestions to result in the claimed invention. Accordingly, we
are not persuaded that the Examiner has failed to provide sufficient
identification of which elements would be combined, and the manner of
such combination, such one having ordinary skill in the art would not have
found the combination to render obvious the claimed invention. As such,
Appellants have not shown persuasively that the Examiner has failed to set
forth a prima facie case of unpatentability for lack of presenting a prima
facie case of unpatentability.
Appellants' second contention is that the combination would not have
been obvious because the Examiner's statement that the combination would
result in a "large ON/OFF ratio" does not show that the resulting ratio would
be improved over that naturally occurring in the invention of Cederbaum.
App. Br. 18-19. However, the Examiner set forth a reason for combining
the teachings of Iwasaki and Cederbaum sufficient to establish a prima facie
case ofunpatentability, as discussed supra. The burden thus shifts to
Appellants to explain why the ON/OFF ratio of Iwasaki would not be
6
Appeal2017-007418
Application 12/906,565
advantageous when used in combination with the limitations of Cederbaum
relied upon in the rejection. Rather than providing a reasoned explanation of
why the ON/OFF ratio would not be advantageous, Appellants merely allege
that any such advantage is "speculative." App. Br. 18-19. Appellants have
not identified any objective evidence, to show that the ON/OFF ratio of
Cederbaum' device is such that it would not be improved. Rather,
Appellants merely provide attorney argument to rebut the Examiner's
reliance on statements in Iwasaki that an advantageous ON/OFF ratio would
motivate the use of the oxide-semiconductor layer as claimed. . It is well
established that the arguments of counsel cannot take the place of evidence
in the record. In re Schulze, 346 F.2d 600, 602 (CCPA 1965).Accordingly,
we are not persuaded by Appellants' contention that the Examiner has not
shown sufficient reasons to combine the Iwasaki and Cederbaum references.
Appellants' third contention is that the combination of references
would result in a device having electrical properties inferior to that of
Cederbaum, and would "go against the CMOS (Complementary Metal
Oxide Semiconductor) technology employed by Cederbaum, which consists
of employing transistors of complementary types (e.g., both P-type and N-
type)." App. Br. 15-18. Appellants contend that it would not be obvious to
modify Cederbaum in such a manner because it would be unsuitable for its
intended purpose. App. Br. 18 (citing In re Gordon, 733 F.2d 900,221
USPQ 1125 (Fed. Cir. 1984). Appellants further argue that the oxide
semiconductor of Iwasaki is inferior, in terms of speed and mobility, to the
polycrystalline semiconductor of Cederbaum such that one would not be
motivated to make such a substitution. We do not find Appellants'
contentions persuasive.
7
Appeal2017-007418
Application 12/906,565
We are not persuaded that the situation presented in Gordon is
apposite to the appealed claims. In Gordon, the Federal Circuit addressed an
obviousness rejection which required the structure of a prior art fluid
filtering device to be turned upside down and have the inlet/outlet
connections altered, in order to make obvious the claimed invention.
Gordon, 733 F.2d at 902. The court noted that because the prior art fluid
filtering device operated with the assistance of gravity, turning the device
upside down would render the device inoperable as a filter. Id. Since the
rejection provided no motivation for turning the device upside down, except
that it could be done to meet the claimed structure, the court found that it
had not been shown to be obvious. Id.
Unlike the situation presented in Gordon, Appellants have not shown
that the teachings or suggestions of Cederbaum would be inoperative if
altered by the teachings or suggestions of Iwasaki. Appellants contend that
Cederbaum is directed to "6T SRAMs" ( citing Figure 1) having 4NFETS
and 2PFETS, and having a "high -ON state current, and thus a high carrier
mobility" as important design considerations. App. Br. 14--18. However,
Appellants do not explain how the invention of Cederbaum would be
inoperative, in the sense of Gordon, if those "design considerations" were
not maintained through incorporation of a semiconductive oxide layer.
Appellants have not established that the purported "important design
considerations" are required elements of Cederbaum such that substitution of
the semi conductive oxide layer of Iwasaki, as set forth by the Examiner,
would render Cederbaum's invention inoperative. Thus, we are not
persuaded that modifying Cederbaum to remove features such as particular
8
Appeal2017-007418
Application 12/906,565
FETs, or to result in changes to the ON state current and carrier mobility,
would render inoperative its principle of operation.
Further distinguishing the facts at issue from the situation in Gordon,
the Examiner presents an additional rationale for combining the teachings of
suggestions of Cederbaum with those of Iwasaki. Supra 4--5. As explained
by the Examiner, Cederbaum, as discussed supra, teaches or suggests a
transistor device in which an upper polysilicon transistor is layered over a
lower polysilicon transistor. Cederbaum. Ans. 2-3; (citing Appeal Br. 14).
Iwasaki teaches or suggests using an oxide semiconductor in a transistor,
and provides advantages for its use. Ans. 3 (citing Iwasaki Abstract). The
Examiner additionally points out that Iwasaki itself "clearly recognized and
suggested" that Iwasaki' s oxide semiconductor layer would have been
predictably used in place of a polysilicon layer as used by Cederbaum. Ans.
7 (citing Iwasaki ,r,r 5-12).
As for the "design considerations" advanced by Appellants, it is not
necessary that the combination of reference achieve all of the same
advantages and features of each individual reference. See, e.g., Cross Med.
Prods., Inc. v. Medtronic Sofamor Danek, Inc., 424 F.3d 1293, 1323, (Fed.
Cir. 2005) ("One of ordinary skill in the art need not see the identical
problem addressed in a prior art reference to be motivated to apply its
teachings"); In re Keller, 642 F.2d 413,425 (CCPA 1981) (explaining that
the test for obviousness is "not whether the features of a secondary reference
may be bodily incorporated into the structure of the primary reference," but
instead "what the combined teachings of the references would have
suggested to those of ordinary skill in the art"). Furthermore, we agree with
the Examiner that these "design considerations" are not reflected in the
9
Appeal2017-007418
Application 12/906,565
limitations of the claims. Ans. 5. Accordingly, we are not persuaded of
error in the Examiner's determination that the relied-upon teachings of the
Cederbaum and Iwasaki would have suggested Appellants' claimed
invention to one having ordinary skill in the art.
For the above-mentioned reasons, we sustain the Examiner's rejection
of claim 1. Appellants do not present separate patentability arguments for
any of claims 7-10, 12, 19-22, 24, 3 8, 40-45, and 4 7-51, other than those
raised for independent claim 1. Therefore, we sustain the Examiner's
obviousness rejection of claims. See 37 C.F .R. § 41.37 ( c )(1 )(iv).
Accordingly, we sustain the Examiner's obviousness rejection of claims 1,
7-10, 12, 19-22, 24, 38, 40-45, and 47-51
Claims 3, 15, 27, 32-37, and 52-58
With respect to the rejection of claims 3 and 15 under 35 U.S.C.
§ 103 (a), the issue raised by Appellants is whether the combination of the
teaching or suggestion of Yamazaki to provide a CMOS having a lower p-
type transistor and an upper n-type transistor, with the relied-upon teachings
or suggestions of Iwasaki and of Cederbaum, would have been obvious.
App. Br. 20-21.
The Examiner's rejection states that it would have been obvious to
form a CMOS as from the combined teachings of Iwasaki and of
Cederbaum, as applied to the rejection of claim 1, having a lower p-type
transistor and an upper n-type transistor as taught or suggested by Yamazaki.
Final Act. 13-14. The Examiner reasons that Yamazaki teaches or suggests
that a pair of n-type and p-type transistors could be used in a CMOS in either
10
Appeal2017-007418
Application 12/906,565
configuration of upper and lower transistors. Final Act. 13-14 ( citing
Yamazaki Figs. IA, IB). 3
Appellants contend that the "reference to Yamazaki has not been
shown to predictably combinable with Cederbaum or necessarily overcomes
deficiencies of Cederbaum." App. Br. 20. Appellants further state that no
CMOS reference supports simply reversing the conductivity type of upper
and lower transistors. Id.
We are not persuaded by Appellants' contentions. The Examiner's
interpretation is supported by Yamazaki's description of Figures IA and IB,
which describe an upper n-type/lower p-type in IA, and, "on the other
hand," an upper p-type/lower n-type in Figure IB, in a CMOS embodiment.
Yamazaki ,r,r 60, 166. The person of ordinary skill in the art is "a person of
ordinary creativity, not an automaton." KSR Int'! Co. v. Teleflex Inc., 550
U.S. 398, 421 (2007). Accordingly, we are not persuaded of error in the
Examiner's rationale for combining the teachings or suggestions of
Yamazaki with the teachings or suggestions of Cederbaum and of Iwasaki,
as set forth in the rejection of claims 3 and 15. As such, we sustain the
Examiner's rejection of claims 3 and 15.
With respect to the rejection of claims 27, 32-37, and 55-56 under 35
U.S.C. § I03(a), Appellants contend that the claimed invention is not taught
because Cederbaum and Iwasaki have not been shown to be combinable, and
that Yamazaki does not overcome their deficiencies. Appeal Br. 22.
3 Although the Examiner styles this as an Official Notice, the Examiner
provides support for such Notice with the applied Yamazaki reference itself.
Despite such styling, the rejection is clearly applying the teachings of
Yamazaki for the obviousness rationale.
11
Appeal2017-007418
Application 12/906,565
However, for the reasons set forth in the discussion of the rejections of
claims 1 and 3, supra, we do not find such a contention persuasive.
Accordingly, we sustain the Examiner's rejection of claims 27, 32-37, and
55-56.
With respect to the rejection of claims 52-54 and 57-58 under 35
U.S.C. § 103(a), the issue raised by Appellants is whether the applied
references teach or suggest a planarization layer using aluminum in a
sequence of layers as recited in the claims.
The Examiner relies upon Yamazaki for the teaching or suggestion of
a planarization layer using aluminum. Final Act. 14--1 7 ( citing Yamazaki
Fig. 1 ). The Examiner sets forth how each element of the claims would be
met by elements in one of Cederbaum, Yamazaki, and Iwasaki. Id.
Appellants contend that the Examiner has not met the initial burden of
showing the claimed elements in the sequence shown, and in particular, that
Yamazaki does not teach a planarization layer using aluminum. Appeal Br.
21-22; Reply Br. 9.
The Examiner has set forth a rejection clearly explaining how each
element of the claims would be met by elements in the applied references.
Final Act. 14--17. Appellants have not pointed to any specific error in the
Examiner's explanation of how the elements from each reference would
combine to result in the claimed arrangement of elements, except for
alleging that Yamazaki does not teach a planarization layer using aluminum.
Appeal Br. 21-22; Reply Br. 9. The Examiner has pointed to paragraph 141
of Yamazaki as support for that teaching (Ans. 9), and Appellants have not
provided reasoning as to why the Examiner errs in finding such support
12
Appeal2017-007418
Application 12/906,565
(Reply Br. 9). In view of the Examiner's detailed explanation of the grounds
of rejection, and the lack of any reasoning to the contrary from Appellants
beyond a mere allegation that the sequence of layers is not taught, we are not
persuaded by Appellants' contention of error in the rejections of claims 52-
54 and 57-58. Accordingly, we sustain the Examiner's rejection of claims
52-54 and 57-58.
DECISION
We AFFIRM the Examiner's rejection of claims 1, 3, 7-10, 12, 15,
19-22, 24, 27, 32-38, 40-45, and 47-58 under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
13