XMTT, Inc.

Patent Trials and Appeals Board

May 20, 2020

IPR2020-00143 (P.T.A.B. May. 20, 2020)

Trials@uspto.gov Paper 13
571-272-7822 Date: May 20, 2020

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

INTEL CORPORATION,
Petitioner,
v.
XMTT, INC.,
Patent Owner.

IPR2020-00143
Patent 8,145,879 B2

Before PHILLIP J. KAUFFMAN, MICHELLE N. WORMMEESTER, and
BRENT M. DOUGAL, Administrative Patent Judges.
DOUGAL, Administrative Patent Judge.
DECISION
Denying Institution of Inter Partes Review
35 U.S.C. § 314, 37 C.F.R. § 42.4

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I. INTRODUCTION
A. Background
Intel Corporation (“Petitioner”) filed a Petition to institute an inter
partes review of claims 1–31 (the “challenged claims”) of U.S. Patent
No. 8,145,879 B2 (“the ’879 patent”). Paper 2 (“Pet.”). XMTT, Inc.
(“Patent Owner”) filed a Preliminary Response. Paper 10 (“Prelim. Resp.”).
Under 37 C.F.R. § 42.4(a), we have authority to determine whether to
institute review.
The standard for institution is set forth in 35 U.S.C. § 314(a), which
provides that an inter partes review may not be instituted “unless . . . there is
a reasonable likelihood that the petitioner would prevail with respect to at
least 1 of the claims challenged in the petition.” For the reasons described
below, we conclude that Petitioner has not shown a reasonable likelihood it
would prevail in establishing the unpatentability of at least one of the
challenged claims. We, therefore, do not institute an inter partes review of
the ’879 patent in this proceeding.
B. Related Matters
Petitioner and Patent Owner identify the following litigation involving
the ’879 patent: 1) XMTT, Inc. v. Intel Corporation, 1:18-cv-01810 (D.
Del.). Pet. 64; Paper 6, 2. Patent Owner also identifies IPR2020-0144 as
involving the ’879 patent, and IPR2020-00145 as involving U.S. Patent
No. 7,707,388 B2, which issued from the parent application of the
’879 patent. Paper 6, 2.
C. The ’879 Patent
The ’879 patent is titled “Computer Memory Architecture for Hybrid
Serial and Parallel Computing Systems.” Ex. 1001, code (54). The
’879 patent describes a problem where “[m]any parallel systems are
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engineered to perform tasks with high or massive parallelism, but are not
sufficiently scaleable to effectively support limited parallelism in code, and
in particular, do not efficiently process serial code,” although for many
applications “it is necessary to perform both serial and parallel processing.”
Id. at 1:36–42. To address this problem, the ’879 patent describes “a
computing system including a serial processor and a plurality of parallel
processors configured to switch between serial processing and parallel
processing,” which “provides seamless transitions between parallel and
serial processing modes, while maintaining memory coherence and
providing sufficient performance for streaming applications.” Id. at 1:65–
2:7.
A computing system 100 is depicted in Figure 1, reproduced below.

Figure 1, above, shows a computing system 100
with both serial and parallel processing.
The illustrated system includes “a plurality of memory modules 10, a
plurality of parallel processors 12, a serial processor 14, a serial memory 16,
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and an interconnection network 18.” Id. at 4:37–40. The parallel processors
may include memory, for example “local registers, read-only cache, etc.,”
which “are not private, in that writes cannot be done into them, and data may
be loaded from memory modules 10 through interconnection network 18 to
memory in parallel processors 12.” Id. at 5:10–15. When a switch is made
from serial to parallel processing, “serial processor 14 may send a signal to
parallel processors 12 to indicate an upcoming switch to the parallel
processing mode,” and “parallel processors 12 may start pre-fetching data
and instructions.” Id. at 5:60–67. “The pre-fetched data may be stored in
parallel processors 12 and be ready for quick access once the parallel mode
is entered into.” Id. at 5:67–6:3.
Another computing system 100 is depicted in Figure 3, below.

Figure 3, above, shows another embodiment of computing system 100.
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The illustrated system shows that “[e]ach parallel processor 12 may
include multiple thread control units (TCUs) 300” and that “a TCU 300
includes one or more registers 302.” Id. at 7:26–30. “Registers 302 may be
any local storage in parallel processors 12 and may be read-only.” Id. at
7:31–33. Further,
When a register 302 (such as local cache, register or other
memory for a parallel processor 12) is read-only (such that the
parallel processor 12 may not generally modify the data stored in
the register 302), updated data generated by the parallel
processor 12 may be stored in the register 302 only when the
updated data is also stored in one or more of the shared memory
modules 10 so that the updated data is available to other parallel
processors 12 and/or serial processor 14.

Id. at 7:39–47.
D. Illustrative Claim
Of the challenged claims, 1 and 20 are independent. Each of claims
2–19 and 21–31 depends directly or indirectly from independent claims 1 or
20. Claim 1, below, is representative:
1. An apparatus comprising:
a serial processor to execute instructions in a computing
program primarily in serial;
a first, private memory to store data solely for use by the
serial processor in executing the instructions;
a plurality of parallel processors to execute instructions
in the computing program primarily in parallel, at least one
parallel processor of the plurality of parallel processors having
a second, local read-only memory; and
a plurality of shared memory modules to store data for
use by the plurality of parallel processors in executing the
instructions.
Ex. 1001, 13:62–14:7.
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E. Alleged Grounds of Unpatentability
Petitioner asserts that the challenged claims would have been
unpatentable on the following grounds:1
Claims Challenged 35 U.S.C. § References
1–31 103(a) Wen2, Nakamura3
1–31 103(a) Wen, Koufaty4

II. ANALYSIS
A. Claim Construction
In an inter partes review, a claim “shall be construed using the same
claim construction standard that would be used to construe the claim in a
civil action under 35 U.S.C. § 282(b).” 37 C.F.R. § 42.100(b) (2019); see
Changes to the Claim Construction Standard for Interpreting Claims in Trial
Proceedings Before the Patent Trial and Appeal Board, 83 Fed. Reg. 51,340
(Oct. 11, 2018) (amending 37 C.F.R. § 42.100(b) effective Nov. 13, 2018).
Under this standard, claim terms are given their ordinary and customary
meaning as would have been understood by a person of ordinary skill in the
art at the time of the invention and in the context of the entire patent
disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
2007). If the specification “reveal[s] a special definition given to a claim

1 Petitioner supports its challenge with a Declaration of Dr. David Kaeli.
(Ex. 1014) (“Kaeli Decl.”).
2 Ex. 1003, “Hardware Design, Prototyping and Studies of the Explicit
Multi-Threading (XMT) Paradigm,” (2008) (“Wen”).
3 Ex. 1004, U.S. Pat. App. Pub. 2003/0177273 A1 (Sept. 18, 2003)
(“Nakamura”).
4 Ex. 1005, “Data Forwarding in Scalable Shared-Memory Multiprocessors,”
IEEE Transactions on Parallel and Distributed Systems, Vol. 7, No. 12
(Dec. 1996) (“Koufaty”).
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term by the patentee that differs from the meaning it would otherwise
possess[,] . . . the inventor’s lexicography governs.” Phillips v. AWH Corp.,
415 F.3d 1303, 1316 (Fed. Cir. 2005) (en banc) (citing CCS Fitness, Inc. v.
Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002)). We apply this
standard to the claims of the ’879 patent.
1. “Read-Only Memory”
We construe the claim term “read-only memory” so that we may
assess Petitioner’s assertion that the ’879 patent includes new matter. See
Pet. 1. Specifically, Petitioner asserts that when properly construed, “read-
only memory” is new matter so that the ’879 patent is not entitled to a filing
date earlier than the filing date of March 10, 2010. Id. Our evaluation of
this assertion then permits us to determine if Wen is prior art.
Petitioner offers a construction for the phrase “read-only memory”
which is required by all of the challenged claims. Pet. 12. Specifically,
Petitioner asserts “‘read-only memory’ in the challenged claims means
‘memory for a parallel processor that stores updated data generated by the
parallel processor only when the updated data is already available to other
parallel processors and/or a serial processor.’” Id. (citing Kaeli Decl. ¶¶ 59–
64).
Petitioner explains that “a person of ordinary skill in the art
(“POSITA”) would have typically understood ‘read-only memory’ as
memory that stores data that cannot be updated by a processor.” Id.; see
also id. at 14 (listing dictionary definitions for terms including “read-only”).
However, Petitioner argues that “the ’879 Patent defines ‘read-only
memory’ as a memory storing data that a processor could sometimes update
if certain conditions are met.” Id. at 12–13. Then, more specifically,
Petitioner argues ‘“read-only memory’ in the ’879 Patent is ‘memory for a
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parallel processor that stores updated data generated by the parallel
processor only when the updated data is already available to other parallel
processors and/or a serial processor.” Id. at 15.
Patent Owner counters that rather than construing just “read-only
memory,” the Board should construe “at least one parallel processor . . .
having a local, read-only memory.” Prelim. Resp. 18. Patent Owner argues
that this should be construed to mean “at least one parallel processor having
a memory such that the parallel processor may not generally modify the data
stored therein.” Id. Patent Owner further contends that this definition is
consistent with the ordinary meaning, or alternatively, if it is not, the phase
was redefined in the prior parent patent application. Prelim. Resp. 18, 21.
In order to construe “read-only memory,” including determining
whether the inventor intended to redefine “read-only memory,” we must
review the entire patent disclosure to ensure the claim construction is
consistent with the disclosure as a whole. Markman v. Westview
Instruments, Inc., 517 US 370, 389 (1996) (“the standard construction rule”
requires a “sophisticated analysis of the whole document, . . . [such] that a
term can be defined only in a way that comports with the instrument as a
whole.”). Where the patentee acts as its own lexicographer, it “must be done
with reasonable clarity, deliberateness, and precision . . . so as to give one of
ordinary skill in the art notice of the change.” In re Paulson, 30 F.3d 1475
(Fed. Cir. 1994).
Petitioner, in its claim construction analysis, reviews some of the
relevant disclosure in the ’879 patent. See Pet. 13, 15 (primarily discussing
Ex. 1001, 7:39–47). However, we determine that Petitioner’s analysis is
lacking. Petitioner’s analysis is too narrowly focused on one sentence (Ex.
1001, 7:39–47) without fully considering how that sentence fits in with the
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rest of the ’879 patent. As such, we do not accept Petitioner’s claim
construction of “read-only memory.”5 In the following section, we review
Petitioner’s claim construction analysis and the various teachings of the ’879
patent related to “read-only memory.”
a) Petitioner’s Analysis of the ’879 Patent
Petitioner states that “[t]he ’879 Patent describes a ‘read-only
memory’ as memory in which a processor could sometimes store updated
data generated by the processor” and then lists two examples. Id. at 13.
Petitioner briefly explains that the ’879 patent discloses “that some
processors include local memory, . . . [which] may be ‘read-only’ and that
the “parallel processors pre-fetch data or instructions from shared memory
and store pre-fetched data in local memory.” Id. at 13 (citing Ex. 1001, 5:9–
12, 7:20–24, 7:30–39). Petitioner then argues that the ’879 patent
specification redefines “read-only memory” when it states:
When a register 302 (such as local cache, register or other
memory for a parallel processor 12) is read-only (such that the
parallel processor 12 may not generally modify the data stored in
the register 302), updated data generated by the parallel
processor 12 may be stored in the register 302 only when the
updated data is also stored in one or more of the shared memory
modules 10 so that the updated data is available to other parallel
processors 12 and/or serial processor 14.
Id. (quoting Ex. 1001, 7:39–47). Petitioner summarizes this as “in contrast
to known ‘read-only memory’ at the time, a parallel processor generates and

5 We have reviewed the District Court claim construction from the related
litigation (Ex. 1030) including the Court’s construction of “read-only
memory.” We decline to adopt a construction of “read-only memory”
herein. Further, as noted, we determine that for the purposes of this
proceeding, Petitioner has failed to establish that their construction of “read-
only memory” is correct.
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stores updated data to its read-only memory when that updated data is also
available to other processors.” Id.; see also id. at 15 (restating and
summarizing the same quote (Ex. 1001, 7:39–47) in slightly different
words).
As noted above, this analysis is insufficient to show that the inventor
intended to redefine “read-only memory” as “memory for a parallel
processor that stores updated data generated by the parallel processor only
when the updated data is already available to other parallel processors and/or
a serial processor.” Pet. 12.
b) The Quote (Ex 1001, 7:39–47)
We start our review of Petitioner’s claim construction analysis with
the quote (Ex. 1001, 7:39–47) Petitioner relies on for support that the
patentee intended to redefine “read-only memory.” As discussed below,
there are two main problems with Petitioner’s analysis of this quote.
The first problem is that Petitioner does not explain why they
shortened the quoted language that they argue redefines “read-only memory”
to their chosen claim construction as shown in the below chart:
Quote from the ’879 Patent Relied
on by Petitioner. Pet. 13.
Petitioner’s Claim Construction of
“Read-Only”
“When a register 302 . . . is read-
only . . ., updated data generated
by the parallel processor 12 may
be stored in the register 302 only
when the updated data is also
stored in one or more of the shared
memory modules 10 so that the
“memory for a parallel processor
that stores updated data generated
by the parallel processor only
when the updated data

[unexplained missing language]

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updated data is available to other
parallel processors 12 and/or serial
processor 14.” Ex. 1001, 7:42–47
is already available to other
parallel processors and/or a serial
processor” Pet. 12.
Petitioner takes the position that “already available to other parallel
processors and/or a serial processor” is broader than “stored in one or more
of the shared memory modules” (id. at 16), but does not address why the
patentee clearly intended to redefine “read-only memory” with one condition
and not the other. The quoted language does not clearly indicate a
preference of one condition over the other.
Petitioner also does not address why the patentee clearly intended to
redefine “read-only memory” to include any of the conditions. In one
location of Petitioner’s argument it summarizes the redefinition as “the
’879 Patent defines ‘read-only memory’ as a memory storing data that a
processor could sometimes update if certain conditions are met.” Id. at 12–
13. In this summary, neither “condition” from the quote is identified.
Consistent with this summary by Petitioner, it is not clear that the claim
construction requires a particular condition to be included,6 or why if the
patentee intended to redefine “read-only memory” it intended to redefine it
as narrowly as argued by Petitioner.
The second problem deals with how the quote (Ex 1001, 7:39–47)
introduces “read-only memory.” In the quote, “read-only memory” is
followed by the statement in parenthesis “(such that the parallel processor 12
may not generally modify the data stored in the register 302).” The quote
then follows this set-apart statement with an instance where data can be

6 This is especially true in view of the language of the claims discussed in
more detail below.
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modified in the read-only memory. Petitioner provides no analysis of why
the statement which has been set apart both by “such that” and with
parenthesis should not control any redefinition. Prelim. Resp. 20–21. A
redefinition, based on this statement would not require any specific
conditions to be included in the claim construction.
Further, the Federal Circuit warns that “in determining whether a
statement by a patentee was intended to be lexicographic, it is important to
determine whether the statement was designed to define the claim term or to
describe a preferred embodiment.” E-Pass Techs., Inc. v. 3Com Corp., 343
F.3d 1364, 1369 (Fed. Cir. 2003); see also Prelim. Resp. 22–24. Petitioner’s
claim construction includes a preferred embodiment, but it is not clear that
this embodiment is required by any claim construction or that the patentee
intended to include the embodiment in its understanding of “read-only
memory.”
c) Other Portions of the Detailed Description
As noted previously, Petitioner’s discussion of “read-only memory” in
the ’879 patent in places other than the relied upon quote (Ex. 1001, 7:39–
47) is limited to mentioning that the ’879 patent discloses “that some
processors include local memory, . . . [which] may be ‘read-only’” and that
the “parallel processors pre-fetch data or instructions from shared memory
and store pre-fetched data in local memory.” Pet. 13 (citing Ex. 1001, 5:9–
12, 7:20–24, 7:30–39). However, Petitioner provides no analysis of how
this disclosure or the disclosure as a whole impacts their proposed claim
construction.
First, just as the ’879 patent teaches at 7:39–47, the ’879 patent
teaches in other locations that the read-only memory can load or store new
or updated data. Prelim. Resp. 19–20; see also Ex. 1001, 5:13–15 (“data
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may be loaded from memory modules 10 through interconnection network
18 to memory [e.g. read-only cache] in parallel processors 12.”), 7:30–39
(“a TCU 300 includes one or more registers 302 . . . . Registers 302 may be
any local storage in parallel processors 12 and may be read-only. . . . The
pre-fetched data is retrieved from memory modules 10 and stored in
registers 302.” (emphasis added)). Petitioner acknowledges as much in the
brief introduction when it states “parallel processors pre-fetch data or
instructions from shared memory and store pre-fetched data in local
memory” which memory they state may be read-only. Pet. 13 (citing
Ex. 1001, 7:20–24, 7:30–39). However, contrary to Petitioner’s proposed
claim construction, this “pre-fetch data” does not have to be “data generated
by the parallel processor.” Id. at 13. For example, the ’879 patent teaches
that the pre-fetch data can be “from memory modules 10.” Ex. 1001, 5:13–
14, 5:67. Again, Petitioner provides no analysis of how this disclosure
impacts their proposed claim construction.
It is possible that Petitioner believes that storing pre-fetch data in
read-only memory is consistent with the understanding of “read-only” by a
person of ordinary skill in the art.7 However, if this is the case, Petitioner
provides no explanation of why storing new data in read-only memory in

7 Petitioner later argues that storing pre-fetch data in read-only memory
where discussed in the priority applications would not have been understood
to have modified the meaning of “read-only memory.” See Pet. 19–23.
However, Petitioner never discusses how these disclosures would be
understood in the context of the disclosure of the ’879 patent. Such an
analysis is essential to a proper claim construction. Further, even in the
priority applications Petitioner only addresses individual teachings with
respect to Petitioner’s proposed particular claim construction, rather than
addressing the understanding of one of ordinary skill in the art based on each
application as a whole.
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one instance (pre-fetch data) is within the ordinary meaning, and another
instance (data generated by the parallel processor) is not. Thus, either way,
Petitioner has not provided sufficient analysis of the Specification of the
’879 patent to support its proposed construction.
d) The Claims
Claim construction starts with the claims. Petitioner notes that “read-
only memory” is required by the challenged claims. Pet. 12. Claims 1 and
20, the only independent claims challenged here, both require “at least one
parallel processor of the plurality of parallel processors having a second,
local read-only memory.” Ex. 1001, 14:2–4, 15:22–24. Many of the
dependent claims also add details related to the read-only memory.
For example, dependent claims 9 and 26 include: the “prefetched data
is stored in the second, local read-only memory of the at least one parallel
processor.” Id. at 14:42–44, 15:56–58. As noted previously, the ’879 patent
does not teach that prefetched data must be data generated by the parallel
processor. Thus, these claims do not appear to require “read-only memory”
to be as narrowly construed as proposed by Petitioner.
As another example, dependent claims 2 and 21 include: “the second,
local read-only memory of the at least one parallel processor may store
updated data only when the updated data is also available in at least one
shared memory module of the plurality of shared memory modules.” Id. at
14:8–12, 15:33–37.8 Though not a direct quote, claims 2 and 21 include the
language from the relied upon quote that is missing from Petitioner’s

8 Other claims also refer to the read-only memory, but we need not address
them for purposes of this Decision. See e.g., Ex 1001, 14:15, 15:15, 15:39
(claims 3, 19, 22).

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proposed claim construction discussed above. Of course, a natural result of
storing the updated data in a shared memory module is that it would be
available to other processors, as taught by the relied upon quote from the
’879 patent, which is included in Petitioner’s proposed claim construction.
Petitioner argues that its proposed claim construction of “read-only
memory” properly “encompass[es] the limitations . . . added in dependent
Claim 2.” Pet. 16; id. (“it encompasses a parallel processor storing updated
data in its read-only memory only when that data is already available to
other processors, which may further include storing updated data in shared
memory modules, as recited in Claim 2”). We agree with Petitioner that
“read-only memory” in claim 1 must encompass the usage of that term in
claim 2. However, we do not agree that “read-only memory” should be
limited in the manner proposed by Petitioner. The independent claims do
not include any of the conditions listed in the quote relied upon by Petitioner
(Ex. 1001, 14:2–4, 15:22–24), while claim 2 does, and we should be careful
not to unduly read limitations from the specification into the claims, except
where the patentee has clearly intended to by being its own lexicographer.
See In re Paulson, 30 F.3d 1475, 1480 (Fed. Cir. 1994). We are not
persuaded that the patentee intended to limit “read-only memory” to include
one condition when claim 2 explicitly includes one of the two conditions
which also naturally results in the condition Petitioner would have us read
into the claims.
Further, the structure of the claims appears more consistent with
Petitioner’s summary of: “the ’879 Patent defines ‘read-only memory’ as a
memory storing data that a processor could sometimes update if certain
conditions are met” rather than its proposed claim construction. Id. at 12–
13.
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e) Conclusion
For all of the above reasons, we do not accept Petitioner’s proposed
claim construction of “read-only memory.” At the same time, we decline to
provide an express construction for “read-only memory” or any other terms
in the ’879 patent because we determine that no such construction is
required for the purposes of this Decision. See Wellman, Inc. v. Eastman
Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011) (“[C]laim terms need only
be construed to the extent necessary to resolve the controversy.” (Internal
quotation marks omitted)).
B. Priority Date of the ’879 Patent
The ’879 patent issued from U.S. Pat. App. No. 12/721,252, which is
a continuation-in-part of U.S. Pat. App. No. 11/606,860 (“the ’860
application”) (now U.S. Pat. No. 7,707,388 B2), and which also claims
priority to U.S. Prov. App. No. 60/740,255 (“the ’255 application”).
Ex. 1001, codes (63), (60).
Petitioner contends that under its proposed construction the recitation
of “read-only memory” in the ’879 patent constitutes new matter not present
in the priority patent applications. Pet. 16. This is because it “does not find
written description support in either the ’255 Application or the ’388 Patent
[’860 application].” Id. Specifically, Petitioner argues that “the ’879 Patent
changes the understood meaning of ‘read-only memory’ by explaining that a
parallel processor can generate and store updated data to its read-only
memory when that updated data is already available to other parallel
processors and/or serial processor in the system.” Pet. 19–20 (citing
Ex. 1001, 7:39–47).
As discussed in detail above, we do not accept Petitioner’s proposed
claim construction of “read-only memory.” Petitioner’s argument
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concerning the ’879 patent’s priority date hinges on its incorrect claim
construction of “read-only.” See id. at 16 (“The properly construed ‘read-
only memory’ is new matter that does not find written description support in
either [priority application].”). Petitioner provides no other argument in its
Petition that the ’879 patent is not entitled to its priority date. Thus,
Petitioner has not established or provided a reasonable basis to determine
that claims 1–31 of the ’879 patent are not entitled to their priority date.
C. Claims 1–31 – Alleged Obviousness Over Wen and Nakamura or
Over Wen and Koufaty
Petitioner asserts that the combination of Wen and Nakamura or that
the combination of Wen and Koufaty renders obvious claims 1–31. See
Pet. 24–63. Dr. David Kaeli provides a declaration in support of Petitioner’s
allegations. See generally Kaeli Decl. Patent Owner opposes. See Prelim.
Resp. 38–48. Dr. Murali Annavaram provides a declaration in support of
Patent Owner’s arguments. See generally Annavaram Decl. For the reasons
set forth below, we determine Petitioner has not demonstrated a reasonable
likelihood of prevailing on its assertion that claims 1–31 are unpatentable
over Wen and Nakamura or Wen and Koufaty.
1. Wen
a) Prior Art Status
As discussed above, on this record, Petitioner has not established or
provided a reasonable basis to determine that claims 1–31 the ’879 patent is
not entitled to claim priority to the November 29, 2006, filing date of the
’860 application or the November 29, 2005, filing date of the
’255 application. Therefore, Wen, with a copyright notice of 2008
(Ex. 1003, 3), is not prior art to the ’879 patent.
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b) Conclusion
As Wen has not been established to be prior art, Petitioner has not
demonstrated a reasonable likelihood of prevailing on its assertions that
claims 1–31 are unpatentable based at least in part on Wen.

III. CONCLUSION
For the foregoing reasons, we have determined that there is not a
reasonable likelihood that Petitioner would prevail with respect to at least
one of the claims challenged in the Petition. We therefore do not institute
trial as to any challenged claim or any ground stated in the Petition.

IV. ORDER
In consideration of the foregoing, it is hereby:
ORDERED that the Petition is denied and no trial is instituted.

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FOR PETITIONER:
Kevin McNish
Brian D. Matty
Laurie Stempler
Michael A. Wueste
DESMARAIS LLP
kkm-ptab@desmaraisllp.com
bmatty@desmaraisllp.com
lstempler@desmaraisllp.com
mwueste@desmaraisllp.com

FOR PATENT OWNER:
H. Annita Zhong
Ben Hattenbach
Anthony Rowles
IRELL & MANELLA LLP
hzhong@irell.com
bhattenbach@irell.com
trowles@irell.com