XMTT, Inc.

Patent Trials and Appeals Board

May 20, 2020

IPR2020-00144 (P.T.A.B. May. 20, 2020)

Trials@uspto.gov Paper 12
571-272-7822 Date: May 20, 2020

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE PATENT TRIAL AND APPEAL BOARD

INTEL CORPORATION,
Petitioner,
v.
XMTT, INC.,
Patent Owner.

IPR2020-00144
Patent 8,145,879 B2

Before PHILLIP J. KAUFFMAN, MICHELLE N. WORMMEESTER, and
BRENT M. DOUGAL, Administrative Patent Judges.
DOUGAL, Administrative Patent Judge.
DECISION
Denying Institution of Inter Partes Review
35 U.S.C. § 314, 37 C.F.R. § 42.4

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I. INTRODUCTION
A. Background
Intel Corporation (“Petitioner”) filed a Petition to institute an inter
partes review of claims 1–38 (the “challenged claims”) of U.S. Patent
No. 8,145,879 B2 (“the ’879 patent”). Paper 2 (“Pet.”). XMTT, Inc.
(“Patent Owner”) filed a Preliminary Response. Paper 9 (“Prelim. Resp.”).
Under 37 C.F.R. § 42.4(a), we have authority to determine whether to
institute review.
The standard for institution is set forth in 35 U.S.C. § 314(a), which
provides that an inter partes review may not be instituted “unless . . . there is
a reasonable likelihood that the petitioner would prevail with respect to at
least 1 of the claims challenged in the petition.” For the reasons described
below, we deny the Petition. We, therefore, do not institute an inter partes
review of the ’879 patent in this proceeding.
B. Related Matters
Petitioner and Patent Owner identify the following litigation involving
the ’879 patent: 1) XMTT, Inc. v. Intel Corporation, 1:18-cv-01810 (D.
Del.). Pet. 69; Paper 6, 2. Patent Owner also identifies IPR2020-0143 as
involving the ’879 patent, and IPR2020-00145 as involving U.S. Patent
No. 7,707,388 B2, which issued from the parent application of the
’879 patent. Paper 6, 2.
C. The ’879 Patent
The ’879 patent is titled “Computer Memory Architecture for Hybrid
Serial and Parallel Computing Systems.” Ex. 1101, code (54). The
’879 patent describes a problem where “[m]any parallel systems are
engineered to perform tasks with high or massive parallelism, but are not
sufficiently scaleable to effectively support limited parallelism in code, and
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in particular, do not efficiently process serial code,” although for many
applications “it is necessary to perform both serial and parallel processing.”
Id. at 1:36–42. To address this problem, the ’879 patent describes “a
computing system including a serial processor and a plurality of parallel
processors configured to switch between serial processing and parallel
processing,” which “provides seamless transitions between parallel and
serial processing modes, while maintaining memory coherence and
providing sufficient performance for streaming applications.” Id. at 1:65–
2:7.
A computing system 100 is depicted in Figure 1, reproduced below.

Figure 1, above, shows a computing system 100
with serial and parallel processing.
The illustrated system includes “a plurality of memory modules 10, a
plurality of parallel processors 12, a serial processor 14, a serial memory 16,
and an interconnection network 18.” Id. at 4:37–40. The parallel processors
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may include memory, for example “local registers, read-only cache, etc.,”
which “are not private, in that writes cannot be done into them, and data may
be loaded from memory modules 10 through interconnection network 18 to
memory in parallel processors 12.” Id. at 5:10–15. When a switch is made
from serial to parallel processing, “serial processor 14 may send a signal to
parallel processors 12 to indicate an upcoming switch to the parallel
processing mode,” and “parallel processors 12 may start pre-fetching data
and instructions.” Id. at 5:60–67. “The pre-fetched data may be stored in
parallel processors 12 and be ready for quick access once the parallel mode
is entered into.” Id. at 5:67–6:3.
Another computing system 100 is depicted in Figure 3, below.

Figure 3, above, shows another embodiment of computing system 100.
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The illustrated system shows that “[e]ach parallel processor 12 may
include multiple thread control units (TCUs) 300” and that “a TCU 300
includes one or more registers 302.” Id. at 7:26–30. “Registers 302 may be
any local storage in parallel processors 12 and may be read-only.” Id. at
7:31–33. Further,
When a register 302 (such as local cache, register or other
memory for a parallel processor 12) is read-only (such that the
parallel processor 12 may not generally modify the data stored in
the register 302), updated data generated by the parallel
processor 12 may be stored in the register 302 only when the
updated data is also stored in one or more of the shared memory
modules 10 so that the updated data is available to other parallel
processors 12 and/or serial processor 14.

Id. at 7:39–47.
D. Illustrative Claim
Of the challenged claims, 1, 20, and 32 are independent. Each of
claims 2–19, 21–31, and 33–38 depends directly or indirectly from one of
independent claims 1, 20, or 32. Claim 1, below, is representative:
1. An apparatus comprising:
a serial processor to execute instructions in a computing
program primarily in serial;
a first, private memory to store data solely for use by the
serial processor in executing the instructions;
a plurality of parallel processors to execute instructions
in the computing program primarily in parallel, at least one
parallel processor of the plurality of parallel processors having
a second, local read-only memory; and
a plurality of shared memory modules to store data for
use by the plurality of parallel processors in executing the
instructions.
Ex. 1101, 13:62–14:7.
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E. Alleged Grounds of Unpatentability
Petitioner asserts that the challenged claims would have been
unpatentable on the following grounds:1
Claims Challenged 35 U.S.C. § References
1–3, 14, 15, 18, 19 103(a) Nakaya2, Nakamura3
1–3, 4, 5, 13–15, 18, 19 103(a) Nakaya, Nakamura, Koufaty4
6–9, 16, 20–38 103(a) Nakaya, Nakamura, Koufaty, Vishkin5
10–12, 17 103(a) Nakaya, Nakamura, Vishkin

II. ANALYSIS
A. Legal Standards for Obviousness
A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
between the claimed subject matter and the prior art are such that the subject
matter as a whole would have been obvious at the time of the invention to a
person having ordinary skill in the art. KSR Int’l Co. v. Teleflex, Inc., 550
U.S. 398, 406 (2007). In Graham v. John Deere Co., 383 U.S. 1 (1966), the
Supreme Court set out a framework for assessing obviousness under 35
U.S.C. § 103 that requires consideration of four underlying factual
determinations: (1) the “level of ordinary skill in the pertinent art,” (2) the

1 Petitioner supports its challenge with a Declaration of Dr. David Kaeli.
(Ex. 1114) (“Kaeli Decl.”).
2 Ex. 1103, U.S. Pat. No. 5,978,830 (Nov. 2, 1999) (“Nakaya”).
3 Ex. 1104, U.S. Pat. App. Pub. 2003/0177273 A1 (Sept. 18, 2003)
(“Nakamura”).
4 Ex. 1105, “Data Forwarding in Scalable Shared-Memory Multiprocessors,”
IEEE Transactions on Parallel and Distributed Systems, Vol. 7, No. 12 (Dec.
1996) (“Koufaty”).
5 Ex. 1106, “Explicit Multi-Threading (XMT) Bridging Models for
Instruction Parallelism” (1998) (“Vishkin”).
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“scope and content of the prior art,” (3) the “differences between the prior
art and the claims at issue,” and (4) when in evidence, objective evidence of
non-obviousness, i.e., so-called “secondary considerations” of non-
obviousness such as “commercial success, long-felt but unsolved needs,
failure of others, etc.” Id. at 17–18. The obviousness inquiry further
requires an analysis of “whether there was an apparent reason to combine
the known elements in the fashion claimed by the patent at issue.” KSR, 550
U.S. at 418 (citing In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (requiring
“articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness”)).
At this stage of the proceeding, neither party has presented evidence6
directed to secondary considerations. The remaining Graham factors are
addressed below.
B. Claim Construction
In an inter partes review, a claim “shall be construed using the same
claim construction standard that would be used to construe the claim in a
civil action under 35 U.S.C. § 282(b).” 37 C.F.R. § 42.100(b) (2019); see
Changes to the Claim Construction Standard for Interpreting Claims in Trial
Proceedings Before the Patent Trial and Appeal Board, 83 Fed. Reg. 51,340
(Oct. 11, 2018) (amending 37 C.F.R. § 42.100(b) effective Nov. 13, 2018).
Under this standard, claim terms are given their ordinary and customary
meaning as would have been understood by a person of ordinary skill in the
art at the time of the invention and in the context of the entire patent
disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.

6 Petitioner makes certain assertions about the lack of secondary
considerations, but provides no evidence in support. Pet. 68–69.
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2007). If the specification “reveal[s] a special definition given to a claim
term by the patentee that differs from the meaning it would otherwise
possess[,] . . . the inventor’s lexicography governs.” Phillips v. AWH Corp.,
415 F.3d 1303, 1316 (Fed. Cir. 2005) (en banc) (citing CCS Fitness, Inc. v.
Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002)). We apply this
standard to the claims of the ’879 patent.
Petitioner offers a construction for the phrase “read-only memory” of
independent claims 1 and 20. Pet. 12. Specifically, Petitioner asserts
“‘read-only memory’ in the challenged claims means ‘memory for a parallel
processor that stores updated data generated by the parallel processor only
when the updated data is already available to other parallel processors and/or
a serial processor.’” Id. (citing Kaeli Decl. ¶¶ 59–64).
Patent Owner offers a construction for the phrase “at least one parallel
processor . . . having a local, read-only memory,” namely, that the plain and
ordinary meaning is “at least one parallel processor having a memory such
that the parallel processor may not generally modify the data stored therein.”
Prelim. Resp. 19. Patent Owner also offers a construction for the phrase
“private [serial] memory,” namely, that “[i]n the context of the ’879 patent, a
private memory is one that only the processor associated with the memory
can access and write to.” Prelim. Resp. 23.
We decline to provide an express construction for any terms in the
’879 patent because we determine that no such construction is required for
the purposes of this Decision. See Wellman, Inc. v. Eastman Chem. Co., 642
F.3d 1355, 1361 (Fed. Cir. 2011) (“[C]laim terms need only be construed to
the extent necessary to resolve the controversy.” (Internal quotation marks
omitted)).
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C. Claims 1–3, 14, 15, 18, 19 – Alleged Obviousness Over Nakaya and
Nakamura
Petitioner asserts that the combination of Nakaya and Nakamura
renders obvious claims 1–3, 14, 15, 18, and 19. See Pet. 16–36. Dr. David
Kaeli provides a declaration in support of Petitioner’s allegations. See
generally Kaeli Decl. Patent Owner opposes. See Prelim. Resp. 24–47.
Dr. Murali Annavaram provides a declaration in support of Patent Owner’s
arguments. See generally Ex. 2001 (Annavaram Decl.). For the reasons set
forth below, we determine Petitioner has not demonstrated a reasonable
likelihood of prevailing on its assertion that claims 1–3, 14, 15, 18, 19 are
unpatentable over Nakaya and Nakamura.
1. Nakaya (Ex. 1103)
Nakaya is titled “Multiple Parallel-Job Scheduling Method and
Apparatus,” and relates to “a multiple parallel-job scheduling method and
apparatus suitable for parallel or concurrent execution of a plurality of
parallel information processing programs.” Ex. 1103, code (54), 1:6–9.
Specifically, Nakaya describes a computer system that includes a group of
processors 1000, where “[t]he processors 1001–1008 are each connected to a
shared memory 2000 to read/write data.” Id. at 7:60–64. “[T]he processor
group is logically categorized . . . in such a manner that, for example, the
processors 1001 to 1004 constitute or behave as multiple serial processors
and the processors 1005 to 1008 constitute or behave as parallel processors.”
Id. at 8:32–37. The processors are connected to a synchronizer 4000 that
includes a synchronization range indicator 4001 that “indicate[s] a
combination of a serial processor and a parallel processor group to assign
individual multiple parallel jobs to the parallel processor group so that the
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parallel processor group may be used commonly for the parallel jobs.” Id. at
8:55–64.
Nakaya’s Figure 1 depicts a computer system with eight processors.

Nakaya’s Figure 1, above, shows an embodiment of a computer system.
Nakaya describes “dynamically changing the number ratio of serial
processors to parallel processors.” Id. at 13:3–6. For example, in an
embodiment, during a time interval T1 to T6, processors 1001 to 1004
behave as serial processors and processors 1005 to 1008 behave as parallel
processors. Id. 13:9–12. But, after T6, “the processor 1001 behaves as a
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serial processor and the processors 1002–1008 behave as parallel
processors.” Id. 13:12–15. Nakaya’s Figure 8 depicts the multiple
execution of parallel jobs.

Nakaya’s Figure 8, above, shows a method changing multiple processors.
In Figure 8, “the OS [operating system] has changed the ratio between
the numbers of processors after time T6.” Id. at 15:29–30.
2. Nakamura (Ex. 1104)
Nakamura is titled “Data Communication Method in Shared Memory
Multiprocessor System,” and relates to “realizing data communication with
coherence being maintained and speed-up of such data communication, and
further to coherence control.” Ex. 1104, code (54), ¶ 1. Specifically,
Nakamura describes that “[i]n a shared memory multiprocessor system
where a plurality of processors share a memory, it is necessary to
communicate shared data between the processors upon executing parallel
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programs.” Id. ¶ 2. In Nakamura’s shared memory multiprocessor system,
each processor “has a register allocated thereto for shared data
communication” and “has a duplicate of the registers of the other
processors.” Id. at 18–19. The contents of registers are communicated via
“ring type network communication channels therebetween.” Id. at 19.
“[O]ne of a plurality of processors is set to be a main processor, and the
other processors are set to be subordinate processors.” Id. at 20.
3. Claim 1
Petitioner asserts that the combination of Nakaya and Nakamura
renders obvious independent claim 1. See Pet. 16–31. In general, Petitioner
relies on the system in Nakaya’s Figures 1, 8, and 9 for showing an
apparatus including a serial processor and parallel processors with shared
memory modules for use by the parallel processors as required by claim 1.
See e.g., id. at 22–23, 24, 29–31. Petitioner asserts that at least the
“[p]rocessor 1001 is a serial processor over the full course of executing the
program” and therefore executes instructions primarily in serial, per claim 1.
Id. at 22–23. Similarly, Petitioner argues that processors 1005–1008 are
parallel processors that execute instructions primarily in parallel because
they are used exclusively as parallel processors in the program illustrated in
Figure 8. Id. at 25.
As noted above, Petitioner relies on Nakaya for the shared memory
modules. However, Petitioner relies on the teachings of Nakamura for many
of the other memory related aspects of claim 1 as will be discussed in more
detail below.
a) Private and Local Memory
Claim 1 requires, inter alia, “a first, private memory to store data
solely for use by the serial processor in executing the instructions,” as well
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as, “at least one parallel processor of the plurality of parallel processors
having a second, local read-only memory.” Ex. 1101, 13:66–67, 14:2–4.
Petitioner acknowledges that Nakaya does not teach “local memories
within its processors” (Pet. 23) and accordingly relies on Nakamura where
private7 or local memories are required by claim 1 (id. at 17–19, 23–24, 26–
29). Petitioner argues that among other benefits, a person of ordinary skill
“would have recognized that incorporating Nakamura’s cache memory . . .
into each of Nakaya’s processors . . . would have provided a faster system.”
Id. at 18 (citing Kaeli Decl. ¶ 93). Thus, Petitioner argues, “[e]ach of
Nakaya’s processors 1001–1008 in Figure 1, modified to include
Nakamura’s local caches, would include its own local memory solely for its
own use.” Id. at 24 (citing Kaeli Decl. ¶¶ 123–124).
Concerning the local read-only memory of claim 1, Petitioner asserts
that ‘“read-only memory’ is ‘memory for a parallel processor that stores
updated data generated by the parallel processor only when the updated data
is already available to other parallel processors and/or a serial processor.’”
Pet. 26.8 Petitioner explains “Nakamura provides a mechanism for updating
shared data in which a processor makes updated data generated by the
processor available to other processors before storing its own copy.” Id. at
20 (citing Ex. 1104 ¶¶ 66–69; Kaeli Decl. ¶ 97). Petitioner further argues
that a person of ordinary skill in the art “would have been motivated to use

7 Patent Owner contests whether a local memory is necessarily private.
Prelim. Resp. 32–33. We do not need to address this issue for purposes of
this Decision.
8 We have reviewed the District Court claim construction from the related
litigation (Ex. 1032) and determine that were we to adopt the Court’s
construction of “read-only memory,” it would not change the results of our
analysis.
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Nakaya’s data transfer areas in a manner similar to Nakamura’s buffers to
hold updated data and commit the updated data to local processor memory
(e.g., cache memory) after the data is available to all processors.” Pet. 21–
22 (citing Ex. 1104 ¶¶ 92–95; Kaeli Decl. ¶ 98.).
However, contrary to Petitioner’s position, the cited passages of
Nakamura do not teach saving updated data to Nakamura’s local cache
memory. Prelim. Resp. 38. For example, Nakamura’s paragraphs 66–69 are
limited to discussing “writing into the shared data registers 10.” Ex. 1104
¶¶ 66, 68. Nakamura’s paragraphs 92–95 are similarly limited. Further,
Nakamura distinguishes between local cache memory and shared memory,
stating that the cache memory 2 “stores data necessary for the associated
processor” while shared memory “stores data . . . required by the respective
processors.” Id. at ¶¶ 37, 39. Petitioner even relies on this distinction in its
reasons to combine Nakamura’s cache memory with Nakaya’s system
stating “[e]ach of Nakaya’s processors 1001–1008 in Figure 1, modified to
include Nakamura’s local caches, would include its own local memory
solely for its own use.” Id. at 24 (citing Kaeli Decl. ¶¶ 123–124) (emphasis
added). Petitioner does not identify any teaching in Nakamura that suggests
writing the updated shared data to the local cache memory.
To the extent that Petitioner is implying that one of ordinary skill in
the art reading Nakamura would have considered modifying Nakamura’s
teachings to ignore the shared data registers and instead write directly to
Nakamura’s cache memory, this is also not supported by the Petition. This
position would appear to be based primarily on hindsight in view of the
claims of the ’879 patent as it is not taught or suggested by Nakaya or
Nakamura. In considering what one of ordinary skill in the art would
understand from a reference, the reference should be considered as a whole.
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In this case, Petitioner provides no explanation as to why one of ordinary
skill in the art would have been motivated to pick and choose portions of the
teachings of Nakamura while ignoring the primary focus (how to update the
shared data registers). See e.g., Ex. 1104, Figs. 3–10. Further, Petitioner
suggests, without sufficient explanation, modifying the teachings of
Nakamura in a manner not contemplated or suggested by Nakamura.
In addition, as noted above, Petitioner relies on Nakamura’s teaching
of local cache memory 2 to modify the system of Nakaya as part of its
analysis to render obvious the claimed local read-only memory of at least
one parallel processor. However, as noted by Patent Owner, Nakamura’s
local cache memory 2 is not read-only, but rather can be written to. Prelim.
Resp. 34 (citing Ex. 1104 ¶ 37 (“Each cache memory (2) allows the
associated processor (1) to read/write a portion of data of the main memory
(4) at high speed, and thus stores data necessary for the associated processor
(1).”). Though Nakamura teaches instances where shared data is only
written to shared memory when it is available to multiple processors,
Petitioner does address why the local cache memory would be further
modified such that data could only be written to the memory in that limited
circumstance as required by their claim construction. Nakamura teaches that
“data necessary for the associated processor” can be freely written to this
memory. Ex. 1104 ¶ 37.
For all of these reasons and based on the current record, Petitioner has
not established a reasonable basis for us to determine that claim 1 would
have been obvious over the combination of Nakaya and Nakamura.
4. Claims 2, 3, 14, 15, 18, 19
Petitioner asserts that the combination of Nakaya and Nakamura
renders obvious claims 2, 3, 14, 15, 18, and 19. See Pet. 32–36. Each of
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claims 2, 3, 14, 15, 18, and 19 depends from claim 1. Thus, Petitioner’s
arguments concerning these claims suffer from the same deficiencies as
claim 1 discussed above. Petitioner has not established a reasonable basis
for us to determine that claims 2, 3, 14, 15, 18, and 19 would have been
obvious over the combination of Nakaya and Nakamura.
D. Claims 1–3, 4, 5, 13–15, 18, 19 – Alleged Obviousness Over Nakaya,
Nakamura, and Koufaty
Petitioner asserts that the combination of Nakaya, Nakamura, and
Koufaty renders obvious claims 1–3, 4, 5, 13–15, 18, and 19. See Pet. 16–
36. Dr. David Kaeli provides a declaration in support of Petitioner’s
allegations. See generally Kaeli Decl. Patent Owner opposes. See Prelim.
Resp. 47–63. Dr. Murali Annavaram provides a declaration in support of
Patent Owner’s arguments. See generally Annavaram Decl. For the reasons
set forth below, we determine Petitioner has not demonstrated a reasonable
likelihood of prevailing on its assertion that claims 1–3, 4, 5, 13–15, 18, and
19 are unpatentable over Nakaya, Nakamura, and Koufaty.
1. Koufaty (Ex. 1105)
Koufaty is titled “Data Forwarding in Scalable Shared-Memory
Multiprocessors,” and relates to the problem that “[s]calable shared-memory
multiprocessors are often slowed down by long-latency memory accesses.”
Ex. 1005 Abstract. Koufaty discloses that data forwarding is a way to
address this problem, such that “when a processor produces a datum, in
addition to updating its cache, it sends a copy of the datum to the caches of
the processors that the compiler identified as consumers of it.” Id. This
way, “when the consumer processors access the datum, they find it in their
caches.” Id. In other words, “when a processor updates a word in its cache,
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it also propagates the update to the caches of processors that are expected to
use the word in the near future.” Id. at 2.
2. Claims 1–3, 4, 5, 13–15, 18, 19
Petitioner asserts that the combination of Nakaya, Nakamura, and
Koufaty renders obvious claims 1–3, 4, 5, 13–15, 18, and 19. See Pet. 16–
36. Petitioner relies on Nakaya and Nakamura for the same disclosures
discussed in the previous ground (see id.), but relies on Koufaty if “read-
only memory” is construed to mean “any memory that a parallel processor
may update as long as updated data is made available to other processors,
either beforehand or afterwards” (id. at 28). This alternative claim
construction is not addressed in Petitioner’s claim construction arguments
(see generally id. at 12–16) and is not further explained elsewhere.
Similar to Nakamura, Koufaty is concerned with updating shared
memory. See e.g., Ex. 1005 Abstract. Petitioner does not rely on Koufaty to
overcome the deficiencies discussed above in the prior ground. Thus,
Petitioner’s arguments including Koufaty suffer from the same deficiencies
as the prior ground discussed above. Thus, we determine Petitioner has not
demonstrated a reasonable likelihood of prevailing on its assertion that
claims 1–3, 4, 5, 13–15, 18, and 19 are unpatentable over Nakaya,
Nakamura, and Koufaty.
E. Claims 10–12, 17 – Alleged Obviousness Over Nakaya, Nakamura,
and Vishkin
Petitioner asserts that the combination of Nakaya, Nakamura, and
Vishkin renders obvious claims 10–12 and 17. See Pet. 67–68. Each of
claims 10–12 and 17 depends from claim 1. Thus, Petitioner’s arguments
concerning these claims suffer from the same deficiencies as claim 1
discussed above. As Petitioner does not rely on Vishkin to overcome these
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deficiencies, Petitioner has not established a reasonable basis for us to
determine that claims 10–12 and 17 are obvious over the combination of
Nakaya, Nakamura, and Vishkin.
F. Claims 6–9, 16, 20–38 – Alleged Obviousness Over Nakaya,
Nakamura, Koufaty, and Vishkin
Petitioner asserts that the combination of Nakaya, Nakamura,
Koufaty, and Vishkin renders obvious claims 6–9, 16, and 20–38. See
Pet. 46–66. Dr. David Kaeli provides a declaration in support of Petitioner’s
allegations. See generally Kaeli Decl. Patent Owner opposes. See Prelim.
Resp. 64–67. Dr. Murali Annavaram provides a declaration in support of
Patent Owner’s arguments. See generally Annavaram Decl.
1. Claims 6–9, 16, 20–31
Similar to claim 1, independent claim 20 also requires “a first, private
memory to store data solely for use by the serial processor in executing the
instructions” and “at least one parallel processor of the plurality of parallel
processors having a second, local read-only memory.” Ex. 1101, 15:19–20,
22–24. In addressing these limitations, Petitioner merely points back to their
positions concerning claim 1. Pet. 56. Claims 6–9 and 16 depend from
claim 1 and claims 21–31 depend from claim 20.
Thus, Petitioner’s arguments concerning these claims suffer from the
same deficiencies as claim 1 discussed above. As Petitioner does not rely on
Vishkin to overcome these deficiencies, Petitioner has not established a
reasonable basis for us to determine that claims 6–9, 16, and 20–31 would
have been obvious over the combination of Nakaya, Nakamura, Koufaty,
and Vishkin.
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2. Claims 32–38
Independent claim 32 does not include all of the same limitations as
claims 1 and 20. For example, claim 32 does not require a parallel processor
with a local read-only memory. See generally, Ex. 1101, 16:20–34.
Claims 33–38 depend from claim 32. Petitioner’s analysis of claim 32 refers
back to other sections of the Petition discussing similar claim elements in
other claims. Pet. 63–64 (e.g., at 63 “Nakaya and Koufaty render obvious
this limitation as discussed in Section VIII.B.2.i.”).
Having determined that Petitioner has not established a reasonable
basis for us to determine that claims 1–31 are unpatentable even with
alternative grounds, we decline to address claim 32 or its dependents,
claims 33–38. Even if Petitioner established a reasonable likelihood of
prevailing with respect to claim 32, instituting a trial with respect to thirty-
eight claims and on four grounds based on evidence and arguments directed
to only six claims and one ground would be an inefficient use of the Board’s
time and resources. See, e.g., Chevron Oronite Co. v. Infineum USA L.P.,
Case IPR2018-00923, slip op. at 10–11 (PTAB Nov. 7, 2018) (Paper 9)
(informative).

III. CONCLUSION
For the foregoing reasons, we have determined that there is not a
reasonable likelihood that the Petitioner would prevail with respect to at
least claims 1–31 of the ’879 patent. Further, pursuant to 35 U.S.C. § 314,
we decline to institute trial as to any challenged claim or any ground stated
in the Petition.

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IV. ORDER
In consideration of the foregoing, it is hereby:
ORDERED that the Petition is denied and no trial is instituted.

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FOR PETITIONER:
Kevin McNish
Brian D. Matty
Laurie Stempler
Michael A. Wueste
DESMARAIS LLP
kkm-ptab@desmaraisllp.com
bmatty@desmaraisllp.com
lstempler@desmaraisllp.com
mwueste@desmaraisllp.com
FOR PATENT OWNER:
H. Annita Zhong
Ben Hattenbach
Anthony Rowles
IRELL & MANELLA LLP
hzhong@irell.com
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