TEXAS INSTRUMENTS INCORPORATED

Patent Trials and Appeals Board

May 12, 2020

2019004149 (P.T.A.B. May. 12, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/985,947 12/31/2015 Abram M. Castro TI-76661 3294
23494 7590 05/12/2020
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, MS 3999
DALLAS, TX 75265
EXAMINER
NGUYEN, DILINH P
ART UNIT PAPER NUMBER
2894
NOTIFICATION DATE DELIVERY MODE
05/12/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ABRAM M. CASTRO and STEVEN KUMMERL
Appeal 2019-004149
Application 14/985,947
Technology Center 2800
Before GRACE KARAFFA OBERMANN, JULIA HEANEY,
BRIAN D. RANGE, Administrative Patent Judges.
RANGE, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 24–41. We have jurisdiction under
35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as Texas
Instruments Incorporated. Appeal Br. 3.
Appeal 2019-004149
Application 14/985,947

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CLAIMED SUBJECT MATTER2
Appellant describes the invention as relating to an integrated circuit
(IC) chip with a vertical connector formed by a vertical wire. Spec. ¶ 1. The
vertical wire could couple to an interconnect on a die. Id. ¶ 4. Figure 3 of the
Specification, reproduced below, illustrates such a wire.

Figure 3 illustrates an example integrated circuit chip of Appellant’s
Specification. Spec. ¶ 10. Vertical wire 102 extends vertically (perpendicular
from the surface of lead 112) through encapsulating material 106 such that
the vertical connector 104 is exposed at the opposite surface. Spec. ¶ 24; see
also id. at ¶ 20 (defining “vertical wire” as “a wire that extends in a direction
normal (e.g., perpendicular) with respect to a surface of the leadframe 56
that forms a surface of the IC chip 50 (e.g., a “bottom” surface of the IC chip
50)”).

2 In this Decision, we refer to the Final Office Action filed December 29,
2017 (“Final Act.”), the Appeal Brief filed May 11, 2018 (“Appeal Br.”), the
Examiner’s Answer dated February 6, 2019 (“Ans.”), and the Reply Brief
filed April 8, 2019 (“Reply Br.”).
Appeal 2019-004149
Application 14/985,947

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Claims 24 and 35 are the only independent claims on appeal. Claim
24 is illustrative and is reproduced below with emphasis added to recitations
determinative of this appeal:
24. An integrated circuit (IC) chip comprising:
a lead frame including a die pad and a plurality of leads;
a die attached to the die pad and electrically connected to
at least one of the plurality of leads;
encapsulating material covering portions of the die and
the lead frame, the encapsulating material forming a first
surface and a second surface of the IC chip, the first surface
coplanar with a surface of the die pad, and the first surface and
second surface being external surfaces of the IC chip; and
a wire electrically connected to and extending from
the at least one of the plurality of leads, the wire protruding
through the second surface beyond a plane of the second
surface.
Appeal Br. 9 (Claims App.). Claim 35 similarly recites, among other things,
“a first wire electrically connected to and extending form the first lead, the
first wire protruding through the second surface beyond a plane of the
second surface.” Id. at 11.
REFERENCES
The Examiner relies upon the prior art below in rejecting the claims
on appeal:
Name Reference Date
Chun

US 5,856,212

Jan. 5, 1999

Greenberg et al.
(“Greenberg”)
US 2006/0247734 A1

Nov. 2, 2006

Chen et al.
(“Chen”)
US 2010/0123226 A1

May 20, 2010

Appeal 2019-004149
Application 14/985,947

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REJECTIONS
The Examiner maintains3 (Ans. 3) the following rejections on appeal:
A. Claims 24 and 27–34 under 35 U.S.C. § 103 as obvious over Chun in
view of Chen. Final Act. 4.
B. Claims 25, 26, and 35–41 under 35 U.S.C. § 103 as obvious over
Chun in view of Chen and further in view of Greenberg. Id. at 6.

OPINION
The Examiner has the initial burden of establishing a prima facie case
of obviousness under 35 U.S.C. § 103. In re Oetiker, 977 F.2d 1443, 1445
(Fed. Cir. 1992) (“[T]he examiner bears the initial burden, on review of the
prior art or on any other ground, of presenting a prima facie case of
unpatentability.”). To establish a prima facie case of obviousness, the
Examiner must show that each and every limitation of the claim is described
or suggested by the prior art or would have been obvious based on the
knowledge of those of ordinary skill in the art or the inferences and creative
steps a person of ordinary skill in the art would have employed. KSR Int’l
Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007); In re Fine, 837 F.2d 1071,
1074 (Fed. Cir. 1988).
To resolve the issues before us on appeal, we focus on the Examiner’s
findings and determinations that relate to the error Appellant identifies. The
Examiner finds that Chun teaches the “wire protruding” as claims 24 and 35

3 In the Answer, the Examiner withdrew rejections based upon other art.
Ans. 3.
Appeal 2019-004149
Application 14/985,947

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recite. Appeal Br. 4. In particular, the Examiner refers to Chun Figure 3A
which we reproduce below.

Chun Figure 3A shows a wire bonding type package. Chun 3:13. Chun
explains that, as depicted in Figure 3A, “holes 14a and 14b communicate[]
with the inner leads 12a of the lead frame 12.” Chun 4:50–5:4. Holes 14a
and 14b “are charged with conductors.” Id. Chun states “[t]he packages
having the conductors in the holes 14a and 14b in turn are processed in a
reflow oven (not shown) for forming of solder balls 15 through reflow
soldering.” Id. Thus, Chun teaches that a plurality of solder balls 15 “are
formed on the holes 14a and 14b.” Id.
Appellant argues that Chun does not teach wires that protrude beyond
a surface of Chun’s semiconductor package. Appeal Br. 6. Appellant’s
argument persuades us of Examiner error. In particular, the preponderance
of the evidence, as explained above, indicates that solder balls 15 are above
the surface of the semiconductor package rather than a wire. The Examiner
takes the position that the conductor in holes 14a and 14b along with solder
ball 15 are a single conductor “wire.” Ans. 5. The Examiner, however, states
that wire should be defined “as a piece of thin conductor/metal thread.” Id. at
6. Even under the Examiner’s proposed claim construction, the Examiner
has not adequately explained why the combination of the conductor in holes
14a and 14b along with solder ball 15 would be a “wire.” See Reply Br. 4.
Appeal 2019-004149
Application 14/985,947

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For example, the Examiner has not persuasively explained why the
conductor and ball combination would be a metal thread. Id. Indeed, the
Specification suggests that Appellant’s wire is distinct from a solder ball.
Spec. ¶ 19 (“Further, a solder ball or solder paste can be applied to the
exposed wire.”).
The Examiner’s treatment of dependent claims, including use of the
Greenberg reference, does not cure this error. We, thus, do not sustain the
Examiner’s rejections.
CONCLUSION
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
24, 27–34 103 Chun, Chen 24, 27–34
25, 26, 35–
41
103 Chun, Chen, Greenberg 25, 26, 35–
41
Overall
Outcome
24–41

REVERSED