Sony Corporation

Patent Trials and Appeals Board

Apr 2, 2021

2019004017 (P.T.A.B. Apr. 2, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/135,749 04/22/2016 Yorito Sakano 880001-5316-US01 8955
165569 7590 04/02/2021
MICHAEL BEST & FRIEDRICH LLP (SONY)
790 N WATER ST
SUITE 2500
MILWAUKEE, WI 53202
EXAMINER
PASIEWICZ, DANIEL M
ART UNIT PAPER NUMBER
2699
NOTIFICATION DATE DELIVERY MODE
04/02/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
DCipdocket@michaelbest.com
nbenjamin@michaelbest.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YORITO SAKANO
Appeal 2019-004017
Application 15/135,749
Technology Center 2600
Before ELENI MANTIS MERCADER, JASON J. CHUNG, and
MICHAEL T. CYGAN, Administrative Patent Judges.
MANTIS MERCADER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 27 and 45–62. See Final Act. 1. We
have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the term “Appellant” to refer to “applicant” as defined in 37 C.F.R.
§ 1.42. Appellant identifies the real party in interest as Sony Corporation.
Appeal Br. 3.
Appeal 2019-004017
Application 15/135,749
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CLAIMED SUBJECT MATTER
The claims are directed to a solid-state image sensor, signal
processing method and electronic apparatus. Claim 27, reproduced below, is
illustrative of the claimed subject matter:
27. An image sensor comprising:
photoelectric conversion part of a semiconductor substrate
that extends into a light receiving part of the semiconductor
substrate from a surface of the semiconductor substrate, a
conductivity-type of the light receiving part is opposite to a
conductivity-type of the photoelectric conversion part;
source/drain regions that extend into the photoelectric
conversion part from the surface of the semiconductor substrate,
the conductivity-type of the photoelectric conversion part is
opposite to a conductivity-type of the source/drain regions;
a first channel region of the photoelectric conversion part
between a first one of the source/drain regions and a second one
of the source/drain regions, the surface of the semiconductor
substrate is between a first gate electrode and the first channel
region;
a second channel region of the photoelectric conversion
part between a third one of the source/drain regions and a fourth
one of the source/drain regions, the surface of the semiconductor
substrate is between a second gate electrode and the second
channel region; and
a third channel region of the photoelectric conversion part
between the fourth one of the source/drain regions and a fifth one
of the source/drain regions, the surface of the semiconductor
substrate is between a third gate electrode and the third channel
region.
REFERENCE
The prior art relied upon by the Examiner is:
Name Reference Date
Inoue US 2006/0208285 A1 Sept. 21, 2006

Appeal 2019-004017
Application 15/135,749
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REJECTION
Claims 27 and 45–62 are rejected under pre-AIA 35 U.S.C. § 102(b)
as being anticipated by Inoue. Final Act. 3.

OPINION
Claim 27
Claim 27 recites “a third channel region of the photoelectric
conversion part between the fourth one of the source/drain regions and a
fifth one of the source/drain regions.” Appeal Br. 30, Claims App. (Claim
27). Appellant explains that Figure 5 of the Specification shows a third
channel region of the photoelectric conversion part between the fourth one
(56) of the source/drain regions and a fifth one (55) of the source/drain
regions, the surface of the semiconductor substrate is between a third gate
electrode (63) and the third channel region. Appeal Br. 8. Modified Figure
5, indicating the third channel region, is reproduced below:

Appeal 2019-004017
Application 15/135,749
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Modified Figure 5 shows a third channel region of the photoelectric
conversion part between the fourth one (56) of the source/drain regions and
a fifth one (55) of the source/drain regions. Appeal Br. 7.
Appellant provides a modified expanded and annotated Figure 8 of
Inoue to show only four source/drain regions. Appeal Br. 8. Modified
Figure 8 is reproduced below:

Modified Figure 8 of Inoue shows only four source/drain regions (not five
source/drain regions as claimed) that are in the second P-type well region
PW2. Appeal Br. 8. Accordingly, we agree with Appellant that Figure 8 of
Inoue fails to depict a third channel region of the photoelectric conversion
part between the fourth one of the source/drain regions and a fifth one of the
source/drain regions, as recited in claim 27.
Appeal 2019-004017
Application 15/135,749
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We also agree with Appellant’s argument that even if the Examiner
relied on Figure 5 of Inoue to show the disputed limitation, in the absence of
a sectional view, Figure 5 fails to depict a photoelectric conversion part of a
semiconductor substrate that extends into a light receiving part of the
semiconductor substrate from a surface of the semiconductor substrate as
required by claim 27. Appeal Br. 10. Figure 5 of Inoue is shown below:

Figure 5 of Inoue is not a sectional view. The Examiner responds:
The Examiner respectfully disagrees with Appellant’s
argument. As can be seen in the fill Fig. 8 of Inoue two
transistors are shown in the PW2 layer above photodiode PHD2
(source follower transistor SF and reset transistor RST). As
stated in paragraph 8 of the Final Office Action mailed
8/14/2018 the Examiner has relied upon the channel region of
the select transistor as being the third channel region of the
claim which is between the fourth and fifth source/drain region
Appeal 2019-004017
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(Note: Inoue abbreviates the select transistor as SL and SLCT
within the disclosure; see paragraph 58 and 74 for example).
Transistor SL is not shown in Fig. 8, but is discussed in
paragraph 74 as having “the second photodiode region PHD2”
“buried below” it. Fig. 5 then shows that the select
transistor (SL) is next to the source follower transistor (SF)
which is next to the reset transistor (RST). Thus, on[e] of
ordinary skill would recognize that when looking at Fig. 8
the select transistor for the first embodiment would be next to
the SF transistor which is next to the RST transistor and they
would all be under PHD2 as explicitly disclosed in
paragraph 74. Therefore, a fifth source/drain region would be
provided (left side of transistor; corresponds to Appellant's
label "source/drain 6" on page 13 of the brief) with
a channel (portion under the gate) and the channel would be
between the fourth source drain region (Applicant concedes this
is at least the left source/drain region of the SF transistor in Fig.
8) and the fifth source/drain region as explained by the
Examiner.
Ans. 5–6 (emphasis added). The Examiner does not address the lack of a
sectional view to show the “photoelectric conversion part of a
semiconductor substrate that extends into a light receiving part of the
semiconductor substrate” and states that this clear from Inoue’s Figures 5
and 8 and paragraph 74. Ans. 6–7.
We agree with Appellant’s argument. The Examiner’s finding that
“Fig. 8 is the cross section that should be referenced with respect to the first
embodiment and Fig. 5. Fig. 8 and the corresponding cited paragraphs by
the Examiner then show the conductivity types and positional relationships
as discussed in detail in the Examiner's rejection” (Ans. 6–7), does not
satisfy the standard required to establish anticipation. Furthermore, relying
on the understanding of what a Figure 8 suggests to one skilled in the art is
not appropriate under anticipation. See Ans. 5–6.

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[U]nless a reference discloses within the four corners of the
document not only all of the limitations claimed but also all of
the limitations arranged or combined in the same way as recited
in the claim, it cannot be said to prove prior invention of the
thing claimed and, thus, cannot anticipate under 35 U.S.C.
§ 102.
Net MoneyIn, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir.
2008).
In examination before the USPTO, the Examiner bears the burden of
presenting a prima facie case for anticipation, of the claimed subject matter.
In re Rinehart, 531 F.2d 1048 (CCPA 1976). The Examiner has not met
their burden to show that Inoue discloses “a third channel region of the
photoelectric conversion part between the fourth one of the source/drain
regions and a fifth one of the source/drain regions” and a “photoelectric
conversion part of a semiconductor substrate that extends into a light
receiving part of the semiconductor substrate from a surface of the
semiconductor substrate” as recited in claim 27.
Accordingly, we reverse the Examiner’s rejection of claim 27.

Claims 45–62
Appellant argues inter alia that independent claim 45 includes a
floating diffusion 54 that extends into a different part of the semiconductor
substrate from the surface of the semiconductor substrate, wherein a first one
of the source/drain regions 59 is electrically connected directly to the
floating diffusion 54. Appeal Br. 18. Appellant argues that “[paragraph 67]
of Inoue discloses that the source region SI of the reset transistor RST is
connected to the floating diffusion region FD via M1C1 and therefore non-
overlap of the second region PHD2 is desirable.” Appeal Br. 19.
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The Examiner’s finding stating
Thus, one of ordinary skill in the art would recognize that
M1C1 of Fig. 8 is a contact hole used to provide the connection
to the floating diffusion which would similarly be required for
the connection of Appellant's invention as the floating diffusion
and source/drain region of the reset transistor are not located in
the same portion of the substrate.

Ans. 15.
[U]nless a reference discloses within the four corners of the
document not only all of the limitations claimed but also all of
the limitations arranged or combined in the same way as recited
in the claim, it cannot be said to prove prior invention of the
thing claimed and, thus, cannot anticipate under 35 U.S.C.
§ 102.
Net MoneyIn, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir.
2008).
We note that while the Examiner is pointing to Figure 8, as
described in paragraph 74, for the direct connection as claimed,
because paragraph 74 states that the cross-sectional structure for the
embodiment of Figure 5 is the same as that for Figure 8. Ans. 15.
However paragraph 74 makes a distinction between certain listed
elements that are the same in both embodiments, and other unlisted
elements that are “substantially the same.” Inoue ¶ 74. Inoue does
not expressly address the connection, unlike other elements expressly
addressed, as being the same in both embodiments, and thus, Figure 8
appears to show a connection that is “substantially” the same. See
para. 74. Although our reviewing court has stated, “[c]ombining two
embodiments disclosed adjacent to each other in a prior art patent
does not require a leap of inventiveness,” the Examiner’s rejection is
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clearly grounded in anticipation, not obviousness. Bos. Sci. Scimed,
Inc. v. Cordis Corp., 554 F.3d 982, 991 (Fed. Cir. 2009). Thus, the
Examiner’s reliance on Figure 8 does not meet the standard of
anticipation requiring identical disclosure. Accordingly, we agree
with Appellant that the Examiner has not shown that Inoue discloses a
direct electrical connection. See Appeal Br. 20.
Should there by further prosecution, we are inviting the
Examiner to consider whether the combined teachings of the separate
embodiments of Inoue including that of paragraph 68 stating “source
region Sl is connected by metal wiring (not shown) to the floating
diffusion region FD” teaches or suggests a direct electrical connection
under obviousness.
Additionally, claim 45, similar to claim 27 recites the limitation
of “a photoelectric conversion part of a semiconductor substrate that
extends into a light receiving part of the semiconductor substrate from
a surface of the semiconductor substrate,” and thus, we also reverse
the Examiner’s rejection for the same reasons as stated above with
respect to claim 27.
Accordingly, we reverse the Examiner’s rejection of claim 45
and for the same reasons the rejections of claims 46–62.
CONCLUSION
The Examiner’s decision to reject claims 27 and 45–62 is
REVERSED.
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Application 15/135,749
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DECISION SUMMARY
Claim(s)
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
27, 45–62 102(b) Inoue 27, 45–62

REVERSED