Smart Modular Technologies Inc.v.Netlist, Inc.

Patent Trial and Appeal Board

Mar 9, 2015

12761179 (P.T.A.B. Mar. 9, 2015)

Trials@uspto.gov Paper 12
571-272-7822 Entered: March 9, 2015

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

SMART MODULAR TECHNOLOGIES INC.,
Petitioner,

v.

NETLIST, INC.,
Patent Owner.

Case IPR2014-01369
Patent 8,516,185 B2

Before LINDA M. GAUDETTE, BRYAN F. MOORE, and
MATTHEW R. CLEMENTS, Administrative Patent Judges.

CLEMENTS, Administrative Patent Judge.

DECISION
Denying Institution of Inter Partes Review
37 C.F.R. § 42.108

IPR2014-01369
Patent 8,516,185 B2

2
I. INTRODUCTION
Smart Modular Technologies Inc. (“Petitioner”) filed a Corrected
Petition requesting inter partes review of claims 1–19 (“the challenged
claims”) of U.S. Patent No. 8,516,185 B2 (Ex. 1007, “the ’185 patent”).
Paper 7 (“Pet.”). Netlist, Inc. (“Patent Owner”) filed a Preliminary
Response. Paper 11 (“Prelim. Resp.”). We have jurisdiction under 35
U.S.C. § 314, which provides that an inter partes review may only be
authorized if “the information presented in the petition . . . and any
[preliminary] response . . . shows that there is a reasonable likelihood that
the petitioner would prevail with respect to at least 1 of the claims
challenged in the petition.” 35 U.S.C. § 314(a). Upon consideration of the
Petition and Preliminary Response, we determine that the information
presented by Petitioner does not establish that there is a reasonable
likelihood Petitioner would prevail in showing the unpatentability of at least
one claim of the ’185 patent. Accordingly, pursuant to 35 U.S.C. § 314, we
deny institution of an inter partes review of claims 1–19 of the ’185 patent.
A. Related Proceedings
Petitioner and Patent Owner indicate that the ’185 patent is involved
in a district court case in the U.S. District Court for the Northern District of
California. Pet. 2–3; Paper 5, 2. The ’185 patent is also involved in SanDisk
Corp. v. Netlist, Inc., Case IPR2014-01029 (PTAB). Pet. 2–3; Paper 5, 2.
B. The ’185 Patent
The ’185 patent relates generally to a memory module that includes a
plurality of memory devices, a controller, and a plurality of circuits that are
configured to selectively isolate the plurality of memory devices from the
IPR2014-01369
Patent 8,516,185 B2

3
system memory controller. Ex. 1007, Abstract. In a conventional memory
module, the system memory controller sees its load during a read or write
operation as all of the memory devices, which causes significant
performance issues. Id. at 4:47–52, 5:5–10, 11:34–38.
To address this need, the ’185 patent discloses a memory module that
employs data transmission circuits to reduce the load seen by the system
memory controller. Id. at 10:41–47. Figure 3A of the ’185 patent is
reproduced below.

Figure 3A depicts an exemplary memory subsystem in accordance with one
embodiment. Id. at 3:37–39. Each memory module 402 comprises multiple
rows, or “ranks,” of memory devices 412, control circuit 430, and a plurality
of data transmission circuits 416. Id. at 7:61–8:13. In the embodiment
depicted, each data transmission circuit 416 is coupled to four memory
devices 412, and is configured to respond to module control signals from
control circuit 430 by selectively allowing or inhibiting data transmission
between system memory controller 420 and at least one selected memory
IPR2014-01369
Patent 8,516,185 B2

4
device. Id. at 8:13–31. System memory controller 420 is coupled to each
memory module 402 by data lines 450 and address and control lines 440. Id.
at 7:34–48. Because data lines 450 are operatively coupled to single data
transmission circuit 416 rather than to four memory devices 412, system
memory controller 420 sees only a single load instead of concurrently seeing
the loads of all four memory devices. Id. at 14:30–59. Thus, in comparison
to prior art memory modules, the load seen by system memory controller
420 can be reduced by a factor of four. Id. at 14:59–62.
C. Illustrative Claim
Of the challenged claims, claims 1 and 13 are independent. Claim 13
is reproduced below:
13. A method of operating a memory module coupled to a
computer system memory controller via a plurality of sets of
data lines, the memory module including a plurality of sets of
memory devices, each set of memory devices corresponding to
a set of data lines, the method comprising:
receiving address/control signals from the memory
controller;
generating first and second sets of module control signals
based on the address/control signals;
transmitting the first set of module control signals to the
plurality of sets of memory devices;
transmitting the second set of module control signals to a
plurality of data transmission circuits distributed across the
memory module, each respective data transmission circuit
corresponding to a respective set of memory devices and
coupled between the respective set of memory devices and a
respective set of data lines, the respective data transmission
circuit including write data paths, read data paths, and control
logic circuitry controlling the write data paths and read data
IPR2014-01369
Patent 8,516,185 B2

5
paths in accordance with the second set of module control
signals; and
during a write operation, using the control logic circuitry
in the respective data transmission circuit to enable a selected
subset of the write data paths in the respective data transmission
circuit in response to the second set of module control signals
such that write data associated with the write operation is
driven from the respective set of data lines to a selected subset
of at least one memory device in the respective set of memory
devices.
Ex. 1007, 20:3–29.
D. References Relied Upon
Petitioner relies upon the following references:
Gower US 7,865,674 B2 Jan. 4, 2011 Ex. 1010
Tsern US 7,464,225 B2 Dec. 9, 2008 Ex. 1011
Best US 8,233,303 B2 July 31, 2012 Ex. 1012
E. The Asserted Grounds of Unpatentability
Petitioner argues that the challenged claims are unpatentable based on
the following grounds:
Reference[s] Basis Claims Challenged
Gower § 102 1–19
Tsern § 102 1–19
Best & Tsern § 103 1–19
II. ANALYSIS
A. Claim Construction
In an inter partes review, claim terms in an unexpired patent are
interpreted according to their “broadest reasonable construction in light of
the specification of the patent” in which they appear. 37 C.F.R. § 42.100(b);
Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14,
IPR2014-01369
Patent 8,516,185 B2

6
2012). Also, claim terms are given their ordinary and customary meaning,
as would be understood by one of ordinary skill in the art in the context of
the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257
(Fed. Cir. 2007).
Petitioner proposes to construe the claim terms
“operable”/“operatively coupled,” “selectively isolate,” “logic circuitry,”
and “module control signal lines extending across a substantial portion of the
memory module.” Pet. 18–21. Patent Owner does not dispute Petitioner’s
proposed claim constructions. Prelim. Resp. 11–14. Patent Owner proposes
to construe “each circuit of the plurality of circuits having a first bit width,”
and “each data transmission circuit has a first bit width.” Prelim. Resp. 12–
14. For purposes of this Decision, we determine only the claim phrases
“operatively coupled” and “selectively isolate” require explicit construction.
1. “operatively coupled”
Independent claim 1 recites “operatively coupled.” Petitioner
proposes that this term be construed to mean “capable of operating
together.” Pet. 18–19 (citing Ex. 1007, 13:9–10, Fig. 4A; Ex. 1008 ¶¶ 25–
29; Ex. 1013, 3; Ex. 1014, 3). Patent Owner does not dispute Petitioner’s
proposed construction.
The ’185 patent states:
In certain embodiments, at least one data transmission circuit
416, 416' selectively switches between two or more memory
devices 412, 412' so as to operatively couple at least one
selected memory device 412, 412' to the system memory
controller 420, 420' (e.g., the data transmission circuit 416, 416'
is configurable to respond to module control signals by
selectively allowing or inhibiting data transmission between the
system memory controller 420, 420' and at least one selected
memory device 412, 412').
IPR2014-01369
Patent 8,516,185 B2

7
Ex. 1007, 11:12–20 (emphases added). The usage of “operatively coupled”
in the ’185 patent is consistent with the extrinsic definition cited by
Petitioner. Pet. 19 (citing Ex. 1014 (IEEE 100 – STANDARD DICTIONARY OF
ELECTRICAL AND ELECTRONIC TERMS (4
th
ed. 1988)). The IEEE definition
of “coupling” in the data transmission context is “the association of two or
more circuits or systems in such a way that power or signal information may
be transferred from one to another.” Ex. 1014. On this record, and for
purposes of this Decision, we determine that the broadest reasonable
interpretation of “operatively coupled” is “associated in such a way that
power or signal information may be transferred from one to another.”
2. “selectively isolate”
Independent claim 1 recites “selectively isolate.” Petitioner proposes
that this term be construed to mean “electrically separating the input of a
component from the output of another component using high impedance.”
Pet. 18–19 (citing Ex. 1007, 13:9–10, Fig. 4A; Ex. 1008 ¶¶ 25–29; Ex. 1013;
Ex. 1014). Patent Owner does not dispute Petitioner’s proposed
construction.
The ’185 patent describes achieving its advantageous result by using
data transmission circuits “to electrically isolate the other memory devices
412 from the memory controller 420 (e.g., the one, two, or more memory
devices 412 to which data is not to be written).” Ex. 1007, 14:39–50.
Petitioner’s proposed construction specifies that the electrical isolation is
achieved “using high impedance.” Although the ’185 patent describes the
disabling of tristate buffers 504 and 506 as “with its output in a high
impedance” condition to, we are not persuaded that the broadest reasonable
interpretation of “selectively isolate” precludes other means of electrically
IPR2014-01369
Patent 8,516,185 B2

8
isolating components. On this record, and for purposes of this Decision, we
determine that the broadest reasonable interpretation of “selectively isolate”
is “electrically separate one component from another.”
B. Claims 1–19 — Anticipation by Gower
Petitioner argues that claims 1–19 are unpatentable under 35 U.S.C.
§§ 102(a) or (e) as anticipated by Gower. Pet. 21–24.
Gower (Exhibit 1010)
Gower describes a memory system that includes a memory hub device
integrated in a memory module. Ex. 1010, Abstract. Figure 3 of Gower is
reproduced below.

IPR2014-01369
Patent 8,516,185 B2

9
Figure 3 depicts a prior art data processing system coupled to a subsystem of
memory modules. Id. at 8:46–47. According to Gower, the bandwidth of
the memory channel feeding each DIMM is significantly larger than the
bandwidth to the memory devices (dynamic RAMs) (“DRAMs”) on the
DIMM, which creates a mismatch in bandwidths. Id. at 2:4–8. In order to
increase the memory bandwidth through a memory module, Gower discloses
a hub with multiple memory device data interfaces that interface between a
memory controller of a processor and memory devices on a memory
module. Id. at 7:37–42. Figure 5A is reproduced below.

Figure 5 depicts a memory system with a buffered memory module that
includes multiple memory device data interfaces in accordance with one
embodiment of Gower. Id. at 12:21–23. Memory hub device 502 includes
link interface 504, memory devices 506, and memory channels 508, 509. Id.
at 12:35–37. Unlike previous memory hubs, which used a single memory
device data interface to access all memory devices, memory hub device 502
uses two memory device data interfaces 510, 511. Id. at 12:35–41. One half
IPR2014-01369
Patent 8,516,185 B2

10
of memory devices 506 are coupled to memory device data interface 510,
and the other half of memory devices 506 are coupled to memory device
data interface 511. Id. at 12:51–58. Memory hub controller 514 responds to
access request packets by driving memory devices 506 responsively using
memory device address and control buses 516 or 517. Id. at 12:63–66.
“Memory hub controller 514 also controls data flow by directing read data
flow selector 518 and write data flow selectors 520, 521.” Id. at 12:66–13:1.
“Memory hub controller 514 uses the address and control information of the
read or write data to control read data flow selector 518 and write data flow
selectors 520, 521 and, thus, multiplexers 550, 540, 541, respectively.” Id.
at 13:1–5.
Analysis
In light of the arguments and evidence, Petitioner has not established a
reasonable likelihood that claims 1–19 are unpatentable as anticipated by
Gower.
Independent claim 1 recites “a controller . . . to produce module
control signals.” Petitioner relies upon Gower’s link interface 504, which
Petitioner argues “receive[s] write request[s arising] from memory controller
532/610 and [] produce[s] address and command information.” Pet. 22
(citing Ex. 1010, 13:21–31, 14:7–13, 15:64–16:1, 13:1–5, Fig. 5, Fig. 6A).
If a memory access request from the memory controller is targeted to
memory devices coupled to the memory hub in which link interface 504
resides, it transmits information
1
to the memory hub controller. Id. at 10:31–

1
Gower describes the link interface as “forward[ing] the write command to
memory hub controller 414 to be executed via internal bus 435” (Id. at

IPR2014-01369
Patent 8,516,185 B2

11
34, 10:59–62, 11:33–36. Otherwise, link interface 504 “re-drive[s] high-
speed memory access requests downstream or upstream on memory channel
409 as applicable using known memory system communication protocols.”
Ex. 1010, 9:47–51.
2
Petitioner identifies the output on memory channel 509
and the output on bus 535, collectively, as the “module control signals.” Pet.
22 (annotated Fig. 5).
Independent claim 1 also recites “a plurality of circuits configured to
receive the module control signals . . . wherein each circuit of the plurality of
circuits is operable, in response to the module control signals.” Petitioner
identifies Gower’s hub 502 as one of the “plurality of circuits,” and a similar
hub downstream as another of the “plurality of circuits.” Pet. 22–25.
3

10:59–62; see id. at 11:33–36) and as “decod[ing] the write requests and
direct[ing] the address and command information to memory hub controller
514 via internal bus 535” (Id. at 13:27–29, 14:13–15). Regardless of
whether the output of link interface 504 on bus 535 is the read/write
command itself or “address and command information” to memory hub
controller 514, that output occurs only if the command is addressed to
memory devices coupled to the memory hub in which link interface 504
resides.
2
Although this passage describes link interface 404 and memory channel
409, link interface 504 and memory channel 509 “operate in a similar
manner to that described with the corresponding element in FIG. 4.”
Ex. 1010, 12:31–35.
3
Petitioner refers to these hubs as hub 604 and hub 606 of Figure 6. Pet.
22–25. As Patent Owner correctly points out, however, hubs 604 and 606
are not arranged in an upstream/downstream configuration. Prelim. Resp.
15–18. Gower discloses explicitly that “downstream memory channel 509
of FIG. 5[] does not connect to memory hub device 606. Rather, memory
hub device 606 connects to independent memory channel 614.” Ex. 1010,
17:19–26. Nevertheless, Gower does describe an embodiment in which a
second hub 502 resides downstream on memory channel 509. We consider

IPR2014-01369
Patent 8,516,185 B2

12
Patent Owner argues that the plurality of memory hubs 502 are not
configured to receive “the module control signals”—i.e., the same “module
control signals”––because “only one memory hub device in the chain of
memory hub devices responds to a particular command from the system
memory controller.” Prelim. Resp. 19. According to Patent Owner:
Gower discloses that the link interface 504 of a particular
memory hub device 502 will direct address and command
information on internal bus 535 to memory hub controller
514—and thus initiate execution of the read or write command
by that memory hub device—only if the read or write command
is targeted to a memory address associated with memory
devices coupled to the memory hub device. In other words, if
the read or write command is not targeted for that memory hub
device 502, the link interface of that memory hub device will
merely forward the command to a downstream memory hub
device to which it is connected—that memory hub device's link
interface 504 will not direct address and command information
on that memory hub device's internal bus 535 to initiate
execution of the read or write command.
Id. at 24. We are persuaded by Patent Owner’s arguments.
In response to any given command, link interface 504 will send a
signal either to memory hub controller 414 via bus 535 or to a downstream
memory hub via memory channel 509. It is not clear how the memory hub
device in which a signal is sent on bus 535 can “receive” a signal that is
generated within itself (i.e., by link interface 504 within that memory hub
device). Even assuming that it can, the signal sent on bus 535 is not
received by the other memory hub device downstream on memory channel
509. Thus, “the module control signals” on bus 535 are not received by “a

Petitioner’s allegations in that context.
IPR2014-01369
Patent 8,516,185 B2

13
plurality of circuits” (emphasis added), as required by claim 1. Likewise, if
link interface 504 forwards address/control information on bus 509 to a
downstream memory hub device, those signals are received only by link
interface 504 of the downstream memory hub device, not by “a plurality of
circuits,” as required by claim 1. Thus, because link interface 504 forwards
the alleged “module control signals” either on bus 535 to the “circuit” within
its memory hub device or on bus 509 to the “circuit” in the downstream
memory hub device, but not to both, Petitioner has not identified “a plurality
of circuits configured to receive the module control signals,” as required by
claim 1.
Independent claim 13 recites “transmitting the first set of module
control signals to the plurality of sets of memory devices.” Petitioner
identifies the information (either the read/write command itself or “address
and control information”) transmitted by link interface 504 on bus 535 to
memory hub controller 514. Pet. 32. Patent Owner argues the output of link
interface 504 on bus 535 is not “transmitt[ed] to the plurality of sets of
memory devices” because it is transmitted only to memory hub controller
514. Prelim. Resp. 28. We are persuaded by Patent Owner’s arguments.
The recited “module control signals”—i.e., the output of link interface
504 on bus 535 and on memory channel 509—are not transmitted to
Gower’s memory devices 506. The signal on bus 535 is sent only to
memory hub controller 514, and the signal sent on memory channel 509 is
transmitted only to a downstream memory hub device. Neither memory hub
controller 514 nor the downstream memory hub device is one of the
“plurality of sets of memory devices,” identified by Petitioner.
IPR2014-01369
Patent 8,516,185 B2

14
Because we are not persuaded that Gower anticipates independent
claims 1 and 13, we also are not persuaded that Gower anticipates dependent
claims 2–12 and 14–19.
Conclusion
On this record, we are not persuaded that Petitioner has established a
reasonable likelihood that it would prevail in showing that claims 1–19 are
unpatentable as anticipated by Gower.
C. Claims 1–19 — Anticipation by Tsern
Petitioner argues that claims 1–19 are unpatentable under 35 U.S.C.
§ 102(b) as anticipated by Tsern. Pet. 34–46.
Tsern
Tsern discloses a memory module with a memory module connector
interface connected to a plurality of integrated circuit buffer devices, each of
which accesses data from an associated plurality of integrated circuit
memory devices. Ex. 1011, Abstract.
Figure 8 is reproduced below.

IPR2014-01369
Patent 8,516,185 B2

15
Figure 8 depicts memory module topology including a plurality of integrated
circuit memory devices and a plurality of integrated circuit buffer devices
with an integrated circuit buffer device for control and address information
and a split control/address signal path. Id. at 1:57–58. Memory module 800
includes buffer device 501 coupled to buffers 100a-d, each of which is
coupled to a set of memory devices 101a-d. Id. at 7:3–8.
Figure 10 is reproduced below.

Figure 10 depicts an embodiment of device 1000 having buffer 100a and a
plurality of memory devices 101a-d. Id. at 8:59–61. “[D]ata (read and/or
write) may be transferred between the plurality of integrated circuit memory
devices 101a-d and buffer 100a on a signal path 1006 (data).” Id. at 8:61–
64. “Signal path 1005 is a bus for providing unidirectional
control/address/clock signals from a buffer 100a to a plurality of integrated
circuit memory devices 101a-d.” Id. at 9:8–11.
IPR2014-01369
Patent 8,516,185 B2

16
Figure 18 is reproduced below.

Figure 18 is a block diagram of buffer device 100a. “Buffer 100a includes
buffer interface 1103a, interfaces 1820a-c, redundancy and repair circuit
1883, multiplexer 1830, request and address logic circuit 1840, data cache
and tags circuit 1860, computations circuit 1865, configuration register set
1881, and clock circuit 1870, singly or in combination.” Id. at 12:54–59.
“In a memory read operation embodiment, buffer 100a receives control
information (including address information) that may be in a packet format
from a master on signal path 121 and in response, transmits corresponding
signals to one or more, or all of memory devices 101a-d on one or more
signal paths 1005.” Id. at 12:60–65. In a memory write operation, “buffer
100a receives control information (including address information) . . . from a
master on signal path 121 and receives the write data for one or more
IPR2014-01369
Patent 8,516,185 B2

17
memory devices 101a-d . . . from a master on signal path 120a,” and
“transmits corresponding signals to one or more, or all of memory devices
101a-d on one or more signal paths 1006 so that the write data may be
stored.” Id. at 13:9–17.
In an embodiment, data cache and tags circuit 1860 includes a write
buffer. Id. at 14:37–47.
Analysis
In light of the arguments and evidence, Petitioner has not established a
reasonable likelihood that claims 1–19 are unpatentable as anticipated by
Tsern.
Independent claim 1 recites “a controller configured . . . to produce
module control signals.” Petitioner identifies buffer device 501 as the
recited “controller” and identifies the output of buffer device 501 on bus
121a and on bus 121b as the recited “module control signals.” Pet. 34–35.
Independent claim 1 recites “each circuit of the plurality of
circuits . . . configured . . . to selectively isolate at least one other memory
device of the at least two corresponding memory devices from the system
memory controller in response to the module control signals.” Petitioner
identifies buffers 100a-d as the “plurality of circuits.” Pet. 35–37. Petitioner
identifies pairs of memory devices 101a, 101b of Figure 9 as “the at least
two corresponding memory devices” and identifies memory device 101a of
Figure 10 as the “at least one other memory device.” Id. at 35 (annotated
Figs. 9A, 10). According to Petitioner, “buffers 100a-d utilize[] the cache,
address/control signals from the address/control buffer 501, and multiplexers
to isolate and route (‘selectively allow’ and ‘selectively isolate’) data from
the external master processor to the memory devices.” Id. at 36.
IPR2014-01369
Patent 8,516,185 B2

18
Patent Owner argues that memory device 101a cannot be “at least one
other memory device” of the “at least two corresponding memory devices”
identified by Petitioner because memory device 101a is not one of memory
devices 101a, 101b of Figure 9 identified by Petitioner. Prelim. Resp. 39–
41. According to Patent Owner:
In the Petitioner's mapping, the highlighted memory device (the
alleged “at least one other memory device”) coupled to buffer
100a (the alleged “circuit”) is not a part of the other memory
devices on the memory module (the alleged “at least two
corresponding memory devices”). Additionally, the other
memory devices on the memory module (the alleged “at least
two corresponding memory devices”) are not coupled to buffer
100a (the alleged “circuit”).
Id. at 40. We are persuaded by Patent Owner’s arguments.
The “at least two corresponding memory devices” identified by
Petitioner are three pairs of memory devices 101a, 101b that are coupled to
buffers 100b, 100c, and 100d, respectively. Pet. 35 (annotated Figs. 9A, 10).
In contrast, memory device 101a, as depicted in Petitioner’s annotation, is in
the pair of memory devices 101a, 101b coupled to buffer 100a. Id. Because
one memory device is coupled to buffer 100a and other memory devices are
coupled to different buffers (i.e., buffers 100b, 100c, 100d), the “at least two
corresponding memory devices” identified by Petitioner are not all
“operatively coupled” to a single “circuit” of the “plurality of circuits,” as
required by claim 1. Id.
Memory devices 101a-d are “at least two corresponding memory
devices” to which each buffer 100 is “operatively coupled.” Ex. 1011,
Fig. 10. But even if Petitioner had identified memory devices 101a-d as the
“at least two corresponding memory devices,” we still would not be
IPR2014-01369
Patent 8,516,185 B2

19
persuaded that Tsern discloses claim 1 because buffer 100a does not
“selectively isolate” any of memory devices 101a-d in response to the
module control signals. To the contrary, Tsern discloses that the
“control/address/clock signals” generated by buffer 100a in response to
control, address, and/or clock information from buffer device 501 (i.e., the
recited “module control signals”), is provided on signal path 1005 “to a
plurality of integrated circuit memory devices 101a-d.” Ex. 1011, 9:6–11
(emphasis added). Figure 11 confirms that the same signal (provided by
buffer die 1100a on signal path 1117) is distributed (along signals paths
1116a-d) to every memory device (labeled 1101a-d in Figure 11). Because
buffer 100 sends the same signal to all of memory devices 101a-d, we are
not persuaded that it “selectively isolate[s] at least one” of memory devices
101a-d “in response the module control signals.” Id.
Independent claim 13 recites “generating first and second sets of
module control signals based on the address/control signals.” Petitioner
identifies Tsern’s control, address, and/or clock information received on
signal path 121 as the recited “address/control signals” received from the
memory controller. Pet. 43. Petitioner further identifies control/address
information on signal path 103 (Fig. 8) or 1005 (Fig. 10) to memory devices
101a-d as the recited “first . . . set[] of module control signals,” and
identifies control/address/clock signals sent by buffer device 501 to buffers
100a-b/c-d as the recited “second set[] of module control signals.” Id. at 44.
Patent Owner argues that “the alleged first set of module control
signals are generated based on the alleged second set of module control
signals, not based on address/control signals received from a memory
controller, as claimed.” Prelim. Resp. 44; id. at 41–43. According to Patent
IPR2014-01369
Patent 8,516,185 B2

20
Owner, “only the alleged second module control signals on signal path 121
are generated based on the address and command information received from
the external master processor.” Id. We are persuaded by Patent Owner’s
argument.
The output of buffer 100a—i.e., the alleged “first . . . set[] of module
control signals”—is based on the output of buffer device 501—i.e., the
alleged “second set[] of module control signals.” Ex. 1011, Fig. 8.
Moreover, Tsern’s control, address, and/or clock information received on
signal path 121—i.e., the alleged “the address/control signals”—is received
only by buffer device 501, which “repeats the control, address, and/or clock
information on signal paths 121a-b.” Ex. 1011, 6:39–41. Specifically,
“buffer device 501 receives control information, such as a packet request,
that specifies an access to at least one of the integrated circuit memory
devices 101a-d and outputs a corresponding control signal (on signal path
121a and/or 121b) to the specified integrated circuit memory device.” Id. at
6:47–52. Thus, buffer device 501 is not “generating . . . [a] second set[] of
module control signals” because it is merely forwarding the identical
“address/control signals” it received from the memory controller. Even
assuming that the output of buffer device 501 was a “second set[] of module
control signals” rather than “the address/control signals,” we still would not
be persuaded by Petitioner’s interpretation because, in that case, the alleged
“first . . set[] of module control signals” would be based on the “second set[]
of module control signals” rather than on “the address/control signals,” as
required by the claim.
Independent claim 13 also recites “transmitting the first set of module
control signals to the plurality of sets of memory devices.” Petitioner
IPR2014-01369
Patent 8,516,185 B2

21
identifies all of Tsern’s memory devices 101a-d across all of data slices a-d
on memory module 800 as the recited “plurality of sets of memory devices.”
Pet. 43; Ex. 1008, 250. As discussed above, Petitioner identifies the
control/address information sent by buffer 100a on signal path 103 (Fig. 8)
or 1005 (Fig. 10) to memory devices 101a-d as the recited “first . . . set[] of
module control signals.” Pet. 44. Patent Owner argues that the
control/address information sent by buffer 100a is not “transmitt[ed] . . . to
the plurality of sets of memory devices” because “the alleged ‘first set of
module control signals’ is transmitted by buffer 100a only to memory
devices 101a-d coupled to buffer 100a—it is not transmitted to the other
memory devices 101 coupled to buffers 100b-d.” Prelim. Resp. 47. We are
persuaded by Patent Owner’s arguments.
The output of buffer 100a, identified by Petitioner as the “first . . .
set[] of module control signals” is transmitted only to memory devices
101a–d coupled to that buffer. See, e.g., Ex. 1011, Fig. 8. The output of
buffer 100a is not transmitted to the remainder of the memory devices
identified by Petitioner as comprising “the plurality of sets of memory
devices,” such as those memory devices coupled to buffers 100b–d.
Conclusion
On this record, we are not persuaded that Petitioner has established a
reasonable likelihood that it would prevail in showing that claims 1–19 are
unpatentable as anticipated by Tsern.
D. Claims 1–19 — Obviousness over Best and Tsern
Petitioner argues that claims 1–19 are unpatentable under 35 U.S.C.
§ 103(a) as obvious over Best and Tsern. Pet. 46–59.
IPR2014-01369
Patent 8,516,185 B2

22
Best
Best discloses “[a]n integrated circuit (IC) package [that] includes an
interface die and a separate storage die.” Ex. 1012, Abstract.
Figure 21 is reproduced below.

Figure 21 illustrates memory module 800 having rows of multi-die memory
devices 801 disposed on front and rear faces. Id. at 24:52–55.
Figure 20A is reproduced below.

Figure 20A illustrates an exemplary packaging arrangement used to
encapsulate interface die 701 and a pair of storage die 702 within a multi-die
memory device 725. Id. at 23:24–34.
Figure 22 is reproduced below.

IPR2014-01369
Patent 8,516,185 B2

23
Figure 22 depicts memory subsystem 850 that includes memory controller
870 and a pair of multi-die memory devices 803 disposed in a package-on-
package arrangement. Id. at 25:13–16. Each memory device 803 includes
interface die 855 and single storage die 857 disposed in a stack. Id. at
25:16–18. Memory controller 870 includes control logic die 864 that may
be a dedicated memory controller or an application specific integrated circuit
that includes functions other than, or in addition to, memory control. Id. at
25:27–30.
Analysis
Independent claim 1 recites “each circuit of the plurality of
circuits . . . configured . . . to selectively isolate at least one other memory
device of the at least two corresponding memory devices from the system
memory controller in response to the module control signals.” We are not
persuaded that Tsern teaches this limitation for the reasons discussed above.
Moreover, Petitioner does not cite Best as teaching this limitation. Pet. 47–
48. Specifically, Petitioner contends:
A POSITA would seek to apply the module control signals
from buffer 501 of Tsern ‘225 as the output of the subsystem
memory controller 870 in Best ‘303, thereby providing the
module control signals to the interface die in Best ‘303. Ex.
1008, Bagherzadeh Decl., ¶¶ 113-115. This would enable the
interface die to provide the isolation and routing claimed in
limitations i.h-i. See reasons with respect to Tsern ‘225 from
section V. F. 1, Claim 1, incorporated herein by reference.
Id. at 48. Because we are not persuaded that Tsern teaches this limitation,
and Petitioner does not cite to Best as teaching this limitation, we are not
persuaded that this limitation is taught by the combination of Tsern and Best.
IPR2014-01369
Patent 8,516,185 B2

24
Independent claim 13 recites “generating first and second sets of
module control signals based on the address/control signals.” We are not
persuaded that Tsern teaches this limitation for the reasons discussed above.
Petitioner also relies upon Best to teach this limitation. Specifically,
Petitioner identifies the output of Best’s memory controller 870 as
generating the recited “second set[] of module control signals,” and
identifies command/control signals transmitted by interface die via path 426
to storage die as the recited “first . . . set[] of module control signals.” Pet.
56 (“the on-module subsystem memory controller 870 comprising control
logic/circuitry 864 generates signals responsive to an external memory
controller to enable the transmitter/receiver of the interface dice”), 57 (“Best
‘303 also discloses transmitting from the interface dice, command/control
signals via path 426 to storage dice, which include the storage arrays, and
transmitting signal from the control logic die 864 to the interface dice.”).
Patent Owner argues “the alleged first set of module control signals in
Best are generated based on the alleged second set of module control
signals—they are not generated based on address/control signals received
from the external memory controller.” Prelim. Resp. 54. We are persuaded
by Patent Owner’s arguments.
Only memory controller 870 generates signals based on “the
address/control signals” received from the external memory controller. The
signals generated by Best’s interface die, such as interface die 855, are based
on the output of control logic die 864 of memory controller 870—i.e., the
alleged “second set of module control signals.” Accordingly, we are not
persuaded that the identified sets of module control signals are both
IPR2014-01369
Patent 8,516,185 B2

25
“generat[ed] . . . based on the address/control signals” received from the
memory controller, as required by the claim.
Independent claim 13 recites “transmitting the first set of module
control signals to the plurality of sets of memory devices.” We are not
persuaded that Tsern teaches this limitation for the reasons discussed above.
Petitioner also relies upon Best’s sets of memory arrays 404 as teaching “the
plurality of sets of memory devices” and, as discussed above, identifies
command/control signals transmitted by interface die via path 426 to storage
die as the recited “first . . . set[] of module control signals.” Pet. 55–57.
Patent Owner argues that Best’s command/control signals on path 426
are not transmitted to “the plurality of sets of memory devices” because “the
alleged ‘first set of module control signals,’ is transmitted from interface die
421 to storage die 423, not to storage core 424, which includes the storage
arrays—the alleged ‘memory devices.’” Prelim. Resp. 57. According to
Patent Owner, the alleged “first . . . set[] of module control signals” are to
command decode logic 457, and that “command decode logic 457 decodes
the command and/or address information and generates and transmits newly-
generated signals to storage array 455 via 468.” Id. at 58. We are persuaded
by Patent Owner’s arguments.
Figure 12 of Best is reproduced below.

Figure 12 depicts a detailed embodiment of multi-die memory device 425.
Ex. 1012, 15:10–11. “[S]torage die 431 . . . includes command decode logic
IPR2014-01369
Patent 8,516,185 B2

26
457 (Cmd Decode) to receive command and address information from the
interface die via command/address path 446.” Ex. 1012, 15:25–29. Thus,
the alleged “first set of module control signals”—i.e., the command and
address information transmitted via path 446—is transmitted only to
command decode logic 457, not to the alleged “plurality of memory
devices”—i.e., storage array 455, which contains the memory arrays 404.
Moreover, Petitioner has provided no evidence that the output of command
decode logic 457 would be “the first set of module control signals” received
by command decode logic. As a result, we are not persuaded that the
combination of Best and Tsern teach this limitation.
Conclusion
On this record, we are not persuaded that Petitioner has established a
reasonable likelihood that it would prevail in showing that claims 1–19
would have been unpatentable as obvious over Best and Tsern.
III. CONCLUSION
For the foregoing reasons, we determine that Petitioner has not
established that there is a reasonable likelihood that it would prevail in
establishing the unpatentability of claims 1–19 of the ’185 patent.
IV. ORDER
Accordingly, it is
ORDERED that the Petition challenging the patentability of claims 1–
19 of U.S. Patent No. 8,516,185 is denied and no trial is instituted.
IPR2014-01369
Patent 8,516,185 B2

27
For PETITIONER:

Michael F. Heafey
Sanjiva K. Reddy
KING & SPALDING LLP
mheafey@kslaw.com
sreddy@kslaw.com

For PATENT OWNER:

Mehran Arjomand
David S. Kim
Erol C. Basol
Jean Nguyen
Jonathan Z. Statman
MORRISON & FOERSTER LLP
marjomand@mofo.com
dkim@mofo.com
ebasol@mofo.com
jnguyen@mofo.com
jstatman@mofo.com