Siemens Aktiengesellschaft

Patent Trials and Appeals Board

Oct 30, 2020

2019004050 (P.T.A.B. Oct. 30, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/364,138 06/10/2014 Rene Graf 5029-1225PUS\349677 3906
27799 7590 10/30/2020
COZEN O'CONNOR
277 PARK AVENUE , 20TH FLOOR
NEW YORK, NY 10172
EXAMINER
VICARY, KEITH E
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
10/30/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patentdocket@cozen.com
patentsecretary@cozen.com
patentsorter@cozen.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte RENE GRAF and WOLFGANG HARTMANN

Appeal 2019-004050
Application 14/364,138
Technology Center 2100
____________

Before JOHN A. EVANS, JASON J. CHUNG, and
NORMAN H. BEAMER, Administrative Patent Judges.

EVANS, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision to reject Claims 11–15, 17, and 19–23, which are all of the claims
pending in the present application. Final Act. 1; see also Claims App.,
Appeal Br. 11–14. We have jurisdiction under 35 U.S.C. § 6.
We REVERSE.2

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies the real party in interest as Siemens
AG, Appeal Br. 2.
2 Throughout this Decision, we refer to the Appeal Brief (“Appeal Br.”)
filed November 29, 2018, the Reply Brief (“Reply Br.”) (filed April 8,
2019), the Final Office Action (“Final Act.”) mailed June 5, 2018, the
Examiner’s Answer mailed February 7, 2019, and the Substitute
Specification (“Spec.”) filed August 2, 2018.
Appeal 2019-004050
Application 14/364,138

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STATEMENT OF THE CASE
CLAIMED SUBJECT MATTER
The claims relate to a method for operating a processor. See Claim 1.
CLAIMS
Claims 11 and 19 are independent. Claim 11 is illustrative and
reproduced below:
11. A method for operating a processor comprising:
providing a first program having a first sequence of
commands to the processor;
providing at least one second program having a second
sequence of commands to the processor, the first program
comprising a time-critical section having time-critical
commands;
executing commands from the first program and the at
least one second program in a processor pipeline;
identifying a starting instant of the time-critical section in
the first program; and
inserting a previously stipulated interrupt program into
the at least one second program executing in the processor
pipeline as soon as the starting instant of the time-critical
section in the first program executing in the processor pipeline
is identified, said interrupt program comprising program
instructions for reading of a value from a memory, program
instructions for comparing the read value with a previously
stipulated value, and program instructions for restarting the
interrupt program if the read value and the previously stipulated
value differ.

Appeal 2019-004050
Application 14/364,138

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PRIOR ART
Name3 Reference Date
Nemirovsky US 2002/0062435 A1 May 23, 2002
Armstrong US 6,785,887 B2 Aug. 31, 2004
Saha US 2006/0161738 A1 July 20, 2006
Brune US 2007/0188296 A1 Aug. 16, 2007
Ozer US 2008/0270758 A1 Oct. 30, 2008
Sydow US 2011/0093857 A1 Apr. 21, 2011
REJECTIONS4 AT ISSUE
1. Claims 11–15, 17, 19, and 20 stand rejected under pre-AIA 35
U.S.C. 103(a) as obvious over Nemirovsky, Armstrong, and
Saha. Final Act. 3–13.
2. Claims 21 and 22 stand rejected under pre-AIA 35 U.S.C. 103(a)
as obvious over Nemirovsky, Armstrong, Saha, and Sydow.
Final Act. 13–14.
3. Claims 21 and 22 stand rejected under pre-AIA 35 U.S.C. 103(a)
as obvious over Nemirovsky, Armstrong, Saha, and Ozer. Final
Act. 14–16.
4. Claim 23 stands rejected under pre-AIA 35 U.S.C. 103(a) as
obvious over Nemirovsky, Armstrong, Saha, and Brune. Final

3 All citations herein to the references are by reference to the first named
inventor/author only.
4 The present application was examined under the pre-AIA first to invent
provisions. Final Act 2.
Appeal 2019-004050
Application 14/364,138

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Act. 16.
ANALYSIS
CLAIMS 11–15, 17, 19, AND 20: OBVIOUSNESS OVER
NEMIROVSKY, ARMSTRONG, AND SAHA
Independent Claim 11 recites, inter alia:
inserting a previously stipulated interrupt program into the at
least one second program executing in the processor pipeline as
soon as the starting instant of the time-critical section in the
first program executing in the processor pipeline is identified,
said interrupt program comprising program instructions for
reading of a value from a memory, program instructions for
comparing the read value with a previously stipulated value,
and program instructions for restarting the interrupt program if
the read value and the previously stipulated value differ.
Independent Claim 19 recites commensurate limitations. Appellant contends
the cited art fails to teach or suggest this limitation. Appeal Br. 4. Appellant
argues the Examiner finds the Nemirovsky-Armstrong combination fails to
teach the claimed “interrupt” and cites Saha for this feature. Appeal Br. 5.
The Examiner finds Appellant mischaracterizes the rejection because
the Examiner cited Armstrong for both the interrupt and the content of the
interrupt. Ans. 4 (citing Final Act. 5 citing Armstrong, col. 6, ll. 41–46)
(“Examiner did not acknowledge that the combination of Nemirovsky and
Armstrong failed to teach or suggest the ‘interrupt’ of independent claim 11,
and did not rely on Saha to teach an ‘interrupt’.”). The Examiner further
finds “as explained above, Saha was not cited to teach an ‘interrupt.’ Ans. 5.
Appellant contends, in view of the Answer, the question is what does
Armstrong describe with respect to the content of the interrupt. Reply Br. 3.
Appellant argues that respecting “interrupts,” Armstrong discloses:
Appeal 2019-004050
Application 14/364,138

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According to an exemplary embodiment of the invention, the
following sequence of actions occur (see FIG. 1):
1. An initiating thread sets a location in memory for each other
thread on that processor.
2. The initiating thread then signals an inter-processor interrupt
(IPI) to all other threads on the processor.
3. Each other thread will get control in an interrupt handler
(because of the IPI), where it acknowledges that it has received
the interrupt and then proceeds to spin on the location in
memory that was set for it in step 1. This guarantees that the
thread will not be using any shared resource of the processor.
4. The initiating thread waits for the other threads on the
processor to acknowledge the IPL When all the threads have
acknowledged, the initiating thread knows that it can use the
shared resource.
Armstrong, col. 6, ll. 35–50 (cited by the Examiner). Appellant argues
Armstrong provides a “mere mention of issuing an ‘interrupt,’” but
“Armstrong fails to provide any teachings with respect to the contents of that
interrupt.” Reply Br. 4. Appellant further argues the
combination of the cited references fails to teach or suggest
Appellants’ claimed invention, i.e., at least the step of ‘inserting
a previously stipulated interrupt program into the at least one
second program as soon as a starting instant of the time-critical
section in the first program is identified, said interrupt program
comprising program instructions for . . . .”
Reply Br. 6 (emphasis omitted).
In agreement with Appellant, we fail to find where the cited art
discloses “inserting a previously stipulated interrupt program into the at least
one second program,” as recited in Claim 1. Armstrong discloses an
“initiating thread then signals an inter-processor interrupt (IPI) to all other
threads on the processor” following which “[e]ach other thread will get
control in an interrupt handler.” Armstrong, col. 6, ll. 39–43. But signaling
Appeal 2019-004050
Application 14/364,138

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an inter-processor interrupt is not the same as inserting an interrupt program
into a second program. In view of the foregoing, we decline to sustain the
rejection of Claim 11 and of Claims 12–15 and 17 dependent therefrom.
Appellant argues independent Claim 19 is patentable as reciting
limitation commensurate to those discussed above for Claim 11. Reply Br.
6. We agree that Claim 19 recites limitations commensurate with those
discussed above. The Examiner does not apply the remaining art to teach
the disputed limitation. Ans. 12 (“Examiner’s responses to arguments with
respect to claims 11 and 19 are likewise applicable to the aforementioned
further claims.”). In view of the foregoing, we decline to sustain the
rejection of Claim 19 and of Claims 20–23 dependent therefrom.

CONCLUSION
We reverse the Examiner’s rejections of Claims 11–15, 17, and 19–23
under 35 U.S.C. § 103(a).

DECISION SUMMARY
In summary:
Claims
Rejected
35
U.S.C. §  Reference(s)/Basis Affirmed Reversed
11–15, 17, 19,
20
103 Nemirovsky,
Armstrong, Saha
11–15, 17,
19, 20
21, 22
103 Nemirovsky,
Armstrong, Saha,
Sydow
21, 22
21, 22
103 Nemirovsky,
Armstrong, Saha,
Ozer
21, 22
Appeal 2019-004050
Application 14/364,138

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Claims
Rejected
35
U.S.C. §  Reference(s)/Basis Affirmed Reversed
23
103 Nemirovsky,
Armstrong, Saha,
Brune
23
Overall
Outcome
11–15, 17,
19–23

REVERSED