Semiconductor Energy Laboratory Co., Ltd.

Patent Trials and Appeals Board

Oct 21, 2020

2020000162 (P.T.A.B. Oct. 21, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/656,173 07/21/2017 Shunpei YAMAZAKI 0756-11463 1000
31780 7590 10/21/2020
Robinson Intellectual Property Law Office, P.C.
3975 Fair Ridge Drive
Suite 20 North
Fairfax, VA 22033
EXAMINER
TRAN, TONY
ART UNIT PAPER NUMBER
2894
NOTIFICATION DATE DELIVERY MODE
10/21/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ptomail@riplo.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte SHUNPEI YAMAZAKI, HIDEKAZU MIYAIRI,
KENGO AKIMOTO, and KOJIRO SHIRAISHI1
________________

Appeal 2020-000162
Application 15/656,173
Technology Center 2800
________________

Before BRADLEY W. BAUMEISTER, GREGG I. ANDERSON, and
DAVID J. CUTITTA II, Administrative Patent Judges.

BAUMEISTER, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s final
rejection of claims 12–23, which constitute all of the pending claims.
Appeal Br. 1. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.2

1 Appellant identifies Semiconductor Energy Laboratory Co. Ltd. as the real
party in interest. Appeal Brief filed July 15, 2019 (Appeal Br.”), 3.
2 Oral arguments were heard on October 15, 2020. A transcript of the
proceeding will be added to the record in due course.
Appeal 2020-000162
Application 15/656,173
2
CLAIMED SUBJECT MATTER
Appellant describes the present invention as follows:
It is an object to provide a semiconductor device including
a thin film transistor [(TFT)] with favorable electric properties
and high reliability, and a method for manufacturing the
semiconductor device with high productivity. In an inverted
staggered (bottom gate) thin film transistor, an oxide
semiconductor film containing In, Ga, and Zn is used as a
semiconductor layer, and a buffer layer formed using a metal
oxide layer is provided between the semiconductor layer and a
source and drain electrode layers. The metal oxide layer is
intentionally provided as the buffer layer between the
semiconductor layer and the source and drain electrode layers,
whereby ohmic contact is obtained.
Abstract.
Independent claim 12, reproduced below, illustrates the appealed
claims:
12. A semiconductor device comprising:
a thin film transistor comprising:
a gate electrode;
a gate insulating layer over the gate electrode;
an oxide semiconductor layer over the gate
insulating layer;
a first conductive layer over the oxide
semiconductor layer;
a second conductive layer over the first conductive
layer;
a third conductive layer over the second conductive
layer;
a fourth conductive layer over the oxide
semiconductor layer;
a fifth conductive layer over the fourth conductive
layer; and
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a sixth conductive layer over the fifth conductive
layer; and
an insulating layer over the oxide semiconductor layer, the
insulating layer being in direct contact with a top surface of the
oxide semiconductor layer,
wherein a gap between the first conductive layer and the
fourth conductive layer is smaller than a gap between the second
conductive layer and the fifth conductive layer,
wherein the gap between the first conductive layer and the
fourth conductive layer is smaller than a gap between the third
conductive layer and the sixth conductive layer, and
wherein a top surface of a first portion of the first
conductive layer is in direct contact with the second conductive
layer, and each of a top surface and a side surface of each of both
end portions of the first conductive layer in a channel length
direction of the thin film transistor is not in direct contact with
the second conductive layer.

STATEMENT OF THE REJECTIONS3
Claims 12–14, 22, and 23 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Seo (US 7,507,616 B2; issued Mar. 24, 2009),
Jeong (US 8,698,215 B2; issued Apr. 15, 2014), and Watanabe (US
6,255,706 B1; issued July 3, 2001). Final Action mailed Aug. 15, 2018
(“Final Act.”), 3–8.
Claims 15–21 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Seo, Jeong, Sugihara (US 2006/0244107 A1; published
Nov. 2, 2006), and Watanabe. Final Act. 8–13.

3 The Examiner initially also rejected independent claims 12 and 15 under
35 U.S.C. § 112(a) as failing to comply with the written–description
requirement, but subsequently withdrew that rejection. Cf. Final Act. 3 with
Examiner’s Answer mailed August 27, 2019 (“Ans.”), 3–4.
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Application 15/656,173
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DETERMINATIONS AND CONTENTIONS
The Examiner finds that Seo discloses most of the limitations of
independent claim 12, but does not teach the semiconductor layer can be an
oxide semiconductor comprised of indium, gallium, and zinc. Final Act. 5.
The Examiner finds that Jeong, which also is directed to TFTs,
teaches an active semiconductor layer composed of ZnInGaO. Final Act. 5
(citing Jeong, col. 4, ll. 4–10; FIG. 2H). The Examiner determines that it
would have been obvious to incorporate a ZnInGaO active semiconductor
layer into Seo’s semiconductor device for the purpose of improving the
electrical contact between the active region and the source and drain regions.
Final Act. 5 (citing Jeong, col. 1, ll. 36–43).
In relation to claims 12, the Examiner further finds that the
combination of Seo and Jeong fails to teach each of a top surface and a side
surface of each of both end portions of the first conductive layer in a channel
length direction of the TFT is not in direct contact with the second
conductive layer. Final Act. 5. That is, the combination does not teach a
lower metal sublayer of a multilayer source/drain wiring layer has a
narrower channel-length gap than an upper metal sublayer that is in direct
physical contact with the lower metal sublayer.
In relation to independent claim 23, the Examiner similarly finds that
the combination of Seo and Jeong fails to teach “wherein the first gap is a
distance between an upper end portion of the first metal layer and an upper
end portion of the third metal layer, and the second gap is a distance between
a lower end portion of the second metal layer and a lower end portion of the
fourth metal layer.” Final Act. 8.
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The Examiner finds that the prior-art TFT embodiment of Watanabe’s
Figure 1 teaches the claimed source/drain electrode gap configurations, as
recited in claims 12 and 23. Final Act. 6, 8. The Examiner reasons that it
would have been obvious to include Watanabe’s prior-art TFT electrode
configuration in a combination according to Seo and Jeong “for the purpose
of optimizing the manufacturing process[,] as taught by Watanabe.” Id. at 6.
Appellant presents multiple arguments regarding the obviousness
rejection. For example, Appellant argues that the Examiner’s “generalized
motivation ‘to optimize’ based on Watanabe . . . [is] speculative, non-
specific, and unsupported by any clear evidence in the record.” Appeal
Br. 11. Appellant urges that the stated motivation, “instead appears only
achievable through impermissible hindsight of Appellant’s disclosure.” Id.
Appellant presents similar arguments in relation to independent
claim 23 for why the Examiner has not established that one of ordinary skill
would have been motivated to combine the cited references in the manner
claimed. Appeal Br. 14–16.

STANDARD OF REVIEW
The Board conducts a limited de novo review of the appealed
rejections for error based upon the issues identified by Appellant, and in
light of the arguments and evidence produced thereon. Ex parte Frye,
94 USPQ2d 1072, 1075 (BPAI 2010) (precedential).

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FINDINGS OF FACT
The record supports the following Findings of Fact (Fact) by a
preponderance of the evidence:
1. Seo’s Figure-2 embodiment is directed to a multilayer bottom-gate
TFT structure with a gate that is formed of a first layer of an aluminum alloy
and a second layer of chromium, molybdenum, or molybdenum alloy. Seo,
col. 4, ll. 14–23. The source/drain wiring layer 173/175 are formed of a
Mo/Al/Mo multilayer structure on top of hydrogenated amorphous silicon.
Seo, col. 4, ll. 38–44; col. 5, ll. 6–24.
2. Jeong is directed to a top-gate TFT structure with an oxide
semiconductor active layer. Jeong, col. 2, ll. 20–24. Jeong’s source-drain
electrodes may be formed of various metals such as Al, Mo, W, Cr, Ni, ITO,
IZO, and alloys thereof on an interlayer insulating layer 16 of undisclosed
composition. Jeong, col. 5, ll. 17–32.
3. Watanabe’s relied upon prior-art embodiment of Figure 1 is directed
to a bottom-gate TFT, which includes a multilayer source/drain wiring
structure composed of aluminum sandwiched between layers of TiN.
Watanabe, col. 2, ll. 5–7; Figure 1.

ANALYSIS
In reasoning that it would have been obvious to modify Seo and Jeong
based on Watanabe for the purpose of optimizing Seo’s manufacturing
process, the Examiner does not explain what manufacturing processes of Seo
purportedly are being modified, omitted, or substituted. See generally Final
Act. Much less does the Examiner address the differences in the masking or
etch chemistries that would be associated with the respective structures of
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the three cited TFTs. Id.; see FACTS 1–3. As it is unclear how the claimed
structure and its manufacturing process are being modified, it is unclear how
the Examiner is proposing to optimize the process.
To be sure, bottom-gate TFTs and top-gate TFTs generally were well
known art recognized equivalent TFT structures. See generally e.g., US
Classification System, Class 257.49 et seq. “NON-SINGLE CRYSTAL, OR
RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART
OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE
JUNCTION),” available at https://www.uspto.gov/web/patents/
classification/uspc257/sched257.htm. Furthermore, the Examiner does show
all of the claimed structures individually in the references, when combined.
See generally Final Act. And the law is clear that the substitution of art-
recognized equivalent structures or compositions generally is obvious:
When a work is available in one field of endeavor, design
incentives and other market forces can prompt variations of it,
either in the same field or a different one. If a person of ordinary
skill can implement a predictable variation, § 103 likely bars its
patentability. For the same reason, if a technique has been used
to improve one device, and a person of ordinary skill in the art
would recognize that it would improve similar devices in the
same way, using the technique is obvious unless its actual
application is beyond his or her skill.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007). The operative
question in this “functional approach” is thus “whether the improvement is
more than the predictable use of prior art elements according to their
established functions.” Id.
However, the ultimate determination that structures, compositions, or
manufacturing methods are art recognized equivalents is a legal
conclusion—not a factual finding. “[A] rejection cannot be predicated on
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the mere identification . . . of individual components of claimed limitations.
Rather particular findings must be made as to the reason the skilled artisan,
with no knowledge of the claimed invention, would have selected these
components for combination in the manner claimed.” Ecolochem, Inc. v.
Southern Calif. Edison Co., 227 F.3d 1361, 1375 (Fed. Cir. 2000). In the
present case, it appears that the obviousness rejection was a product of
impermissible hindsight reasoning, based upon knowledge gleaned only
from Appellant’s disclosure. In re McLaughlin, 443 F.2d 1392, 1395,
(CCPA 1971).
We agree with Appellant, then, that the Examiner has not set forth a
sufficient factual basis to support the conclusion that one of ordinary skill,
having considered the three cited references, would have been motivated or
had a reasonable suggestion to combine the teachings in the manner claimed.
The Examiner’s asserted rationale of “optimizing the manufacturing process
as taught by [Watanabe]” is a merely a bald legal conclusion, unsupported
by any reasonable factual basis.
Accordingly, we reverse the Examiner’s obviousness rejection of
independent claims 12 and 23, as well as claims 13, 14, and 22, which
depend from claim 12.
With respect to the remaining obviousness rejection of claims 15–21,
claim 15 recites language regarding the source/drain electrodes that is
similar to the language of claim 12, recited above. The Examiner does not
rely on Sugihara to cure the deficiencies of the obviousness rejection of
claim 12, explained above. Final Act. 8–13. Accordingly, we likewise
reverse the obviousness rejection of independent claim 15 and also claims
16–21, which depend from claim 15.
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DECISION SUMMARY
In summary:

REVERSED

Claims
Rejected
35 U.S.C. § Basis Affirmed Reversed
12–14, 22, 23 103 Seo, Jeong,
Watanabe
12–14, 22, 23
15–21 103 Seo, Jeong,
Sugihara,
Watanabe
15–21
Overall
Outcome
12–23