SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCDownload PDFPatent Trials and Appeals BoardOct 22, 20212021001162 (P.T.A.B. Oct. 22, 2021) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/364,715 11/30/2016 Francis J. CARNEY ONS02059P01US 5164 132194 7590 10/22/2021 SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (AS) 5005 E. McDowell Road Maildrop A700 Phoenix, AZ 85008 EXAMINER JEAN BAPTISTE, WILNER ART UNIT PAPER NUMBER 2899 NOTIFICATION DATE DELIVERY MODE 10/22/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): ipdocket@iptech.law patents@onsemi.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte FRANCIS J. CARNEY and MICHAEL J. SEDDON Appeal 2021-001162 Application 15/364,715 Technology Center 2800 Before TERRY J. OWENS, CATHERINE Q. TIMM, and MICHAEL P. COLAIANNI, Administrative Patent Judges. OWENS, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), the Appellant appeals from the Examiner’s decision to reject claims 1–5, 7–11, 13, 21–25, and 27.1 We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. The Appellant identifies the real party in interest as Semiconductor Components Industries, LLC (Appeal Br. 2). Appeal 2021-001162 Application 15/364,715 2 CLAIMED SUBJECT MATTER The claims are directed to methods for making a semiconductor device. Claims 1, 7, and 21, reproduced below, are illustrative of the claimed subject matter: 1. A method of making a semiconductor device, comprising: providing a first substrate and a second substrate; providing a third substrate including an active surface; and coupling a side surface of the first substrate substantially perpendicular to a major surface of the third substrate; and coupling a side surface of the second substrate substantially perpendicular to a major surface of the third substrate; wherein a major surface of the first substrate is substantially parallel with and separated from a major surface of the second substrate in an open configuration to achieve fluid flow. 7. A method of making a semiconductor device, comprising: forming a 3D semiconductor package with a plurality of interconnected modular units, wherein a first modular unit comprising a major surface is coupled between a second modular unit and a third modular unit each with a major surface oriented substantially perpendicular to the first modular unit, the first modular unit including an active circuit; and electrically connecting the modular units through one or more conduction paths within the first modular unit, the second modular unit, and the third modular unit; wherein the major surfaces of the second modular unit are separated from each other by a fluid; and wherein the major surfaces of the third modular unit are separated from each other by a fluid. 21. A method of making a semiconductor device, comprising: Appeal 2021-001162 Application 15/364,715 3 coupling a side surface of a first component substantially perpendicular to a major surface of a second component forming a T-shape; wherein the first component comprises a first active circuit; wherein the second component comprises a second active circuit; and wherein the first component is interconnected to the second component to form a 3D semiconductor package. REFERENCES The prior art relied upon by the Examiner is: Name Reference Date Beilin US 5,544,017 Aug. 6, 1996 Hock US 2007/0281077 A1 Dec. 6, 2007 Haensch US 2012/0129276 A1 May 24, 2012 Camarota US 2014/0049932 A1 Feb. 20, 2014 REJECTIONS The claims stand rejected as follows: 1) claims 1, 2, and 5 under 35 U.S.C. § 102(a)(1) over Hock; 2) claims 7, 8, and 11 under 35 U.S.C. § 102(a)(1) over Beilin; 3) claims 21–25 under 35 U.S.C. § 102(a)(1) over Camarota; 4) claims 3 and 4 under 35 U.S.C. § 103 over Hock in view of Camarota; 5) claims 9 and 10 under 35 U.S.C. § 103 over Beilin in view of Camarota; 6) claim 13 under 35 U.S.C. § 103 over Beilin in view of Haensch; and 7) claim 27 under 35 U.S.C. § 103 over Camarota in view of Haensch. OPINION Rejections under 35 U.S.C. § 102(a)(1) The Examiner has the initial burden of establishing a prima facie case of anticipation by pointing out where all of the claim limitations appear in a Appeal 2021-001162 Application 15/364,715 4 single reference. See In re Spada, 911 F.2d 705, 708 (Fed. Cir. 1990); In re King, 801 F.2d 1324, 1327 (Fed. Cir. 1986). Rejection of claims 1, 2, and 5 over Hock We need address only the sole independent claim among claims 1, 2, and 5, i.e., claim 1. Hock discloses a method for making an integrated circuit flip-chip package, comprising placing substrates (23a, 23b) back-to-back such that their circuitry-containing front faces (20a, 20b) carry dies (21a, 21b) directed in opposite directions (¶ 28; Fig. 2). Hock’s Figure 2 is reproduced below: Hock’s Figure 2 depicts the integrated circuit flip-chip package. The Examiner finds that 1) Hock’s Figure 2 shows two dies 21a, one of which corresponds to the Appellant’s first substrate and the other of which corresponds to the Appellant’s second substrate, 2) Hock’s substrate 23a corresponds to the Appellant’s third substrate, and 3) the side surface of Hock’s die 21a, the bottom surface of which is coupled by a ball grid array to substrate 23a’s circuitry-containing front face (20a), is substantially perpendicular to a major surface of substrate 23a (Final 2–3, 10). The Appellant’s claim 1 requires “coupling a side surface of the second substrate substantially perpendicular to a major surface of the third substrate.” The surface of Hock’s die 21a that is coupled to a major surface Appeal 2021-001162 Application 15/364,715 5 of substrate 23a is parallel to that major surface, not perpendicular to it. “[D]uring examination proceedings, claims are given their broadest reasonable interpretation consistent with the specification.” In re Translogic Tech. Inc., 504 F.3d 1249, 1256 (Fed. Cir. 2007) (quoting In re Hyatt, 211 F.3d 1367, 1372 (Fed. Cir. 2000)). The Appellant’s Specification shows and describes that the side surface is both coupled to a major surface of the third substrate and is substantially perpendicular to it (¶¶ 50, 52; Figs. 15a, 15b). The Examiner does not establish that the broadest reasonable interpretation of the Appellant’s above-stated claim limitation encompasses coupling one surface of the second substrate to the third substrate such that a different surface of the second substrate is substantially perpendicular to a major surface of the third substrate.2 Rejection of claims 7, 8, and 11 over Beilin Beilin discloses a multichip module (10) comprising a plurality of integrated circuit (IC) chips (20) flip-chip mounted directly onto the surface of a multichip module (50) consisting of thin film structure (30) that has been formed on the surface of a support base (40) (col. 5, l. 65 – col. 6, l. 3; Fig. 1). The primary power distribution is provided by power bars (60) mounted on the underside of the support base (40) directly below rows of IC chips (20) such that the distance between the power bars (60) and IC chips is minimized (col. 6, ll. 29–36). Power is routed from the power bars (60) to 2 The Examiner’s finding regarding the Appellant’s claim 1 requirement that “a major surface of the first substrate is substantially parallel with and separated from a major surface of the second substrate in an open configuration to achieve fluid flow” is not sufficiently clear for us to address it (Ans. 3). Appeal 2021-001162 Application 15/364,715 6 the IC chips (20) using vias (70) formed through the support base (40), then through vias in the thin film structure (30) (col. 6, ll. 36–40). Beilin’s Figure 1 is reproduced below: Beilin’s Figure 1 is a cross-sectional view of multichip module 10. The Examiner finds that 1) Beilin’s multichip module (50) corresponds to the Appellant’s first modular unit, 2) Beilin’s IC chips (20) correspond to the Appellant’s second and third modular units, 3) the IC chips are perpendicular to the multichip module (50), and 4) the major surfaces of the IC chips (20) are separated from each other by a fluid (Final 3–4). The Appellant’s claim 7 requires that the major surfaces of the second and third modular units are substantially perpendicular to the first modular unit and are separated from each other by a fluid.3 The Examiner states that “the Appellant does not provide a special definition of so called ‘side surface’ and ‘major surface’, and Examiner asserts that fig. 1 of Beilin, col. 7, ln 43+, indicate that the stacked substrates of the present invention form enclosed cooling channels between adjacent layers” (Ans. 4). The Examiner does not establish that the side surfaces of Beilin’s IC chips (20) (which the Examiner relies upon as corresponding to the major 3 Claims 8 and 11 depend from claim 7. Appeal 2021-001162 Application 15/364,715 7 surfaces of the Appellant’s second and third modular units substantially perpendicular to the multichip module (50) relied upon by the Examiner as corresponding to the Appellant’s first modular unit) are the chip (20)’s major surfaces according to the broadest reasonable interpretation of the claim term “the major surfaces” consistent with the Appellant’s Specification. Rejection of claims 21–25 over Camarota Camarota discloses an IC structure (100) comprising side-by-side dies (110, 115) electrically coupled by solder bumps (205) to an interposer (105) which is electrically coupled by vias (225) and solder bumps (220) to a substrate (235) such as a multi-die IC package (¶¶ 33, 38, 39; Fig. 2). Camarota’s Figure 2 is reproduced below: Camarota’s Figure 2 is a cross-sectional side view of IC structure 100. Claim 21 requires “coupling a side surface of a first component substantially perpendicular to a major surface of a second component forming a T-shape.”4 The Examiner finds that Camarota discloses “coupling a side surface of a first component (110) substantially perpendicular to a major surface of a second component (105) forming a T-shape (as seen in fig. 2)” (Final 5) and 4 Claims 22–25 depend directly or indirectly from claim 21. Appeal 2021-001162 Application 15/364,715 8 “fig. 1 of Camaro [sic], shows for example, item 125 and 110 would form a T-shape” (Ans. 4). Camarota’s die 125 is part of die 115 which is side-by-side with die 110, both of which are electrically coupled along a major surface thereof by solder bumps (205) to a major surface of the interposer (105) (¶¶ 22, 26, 33; Figs. 1, 2). The Examiner does not establish that the coupling of die 110 to interposer 105 forms a T-shape according to the broadest reasonable interpretation of that claim term consistent with the Appellant’s Specification. Rejections under 35 U.S.C. § 103 The Examiner does not establish that the claim requirements discussed above with respect to the rejections under 35 U.S.C. § 102(a)(1), which are included in the dependent claims rejected under 35 U.S.C. § 103, would have been prima facie obvious to one of ordinary skill in the art (Final 6–10). CONCLUSION The Examiner has not established a prima facie case of anticipation or obviousness of the method claimed in any of the Appellant’s claims. The Examiner’s rejections, therefore, are reversed. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 2, 5 102(a)(1) Hock 1, 2, 5 7, 8, 11 102(a)(1) Beilin 7, 8, 11 21–25 102(A)(1) Camarota 21–25 3, 4 103 Hock, Camarota 3, 4 9, 10 103 Beilin, Camarota 9, 10 Appeal 2021-001162 Application 15/364,715 9 13 103 Beilin, Haensch 13 27 103 Camarota, Haensch 27 Overall Outcome 1–5, 7–11, 13, 21–25, 27 REVERSED Copy with citationCopy as parenthetical citation