SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Patent Trials and Appeals Board

Oct 4, 2021

2020006616 (P.T.A.B. Oct. 4, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/440,967 02/23/2017 Yusheng LIN ONS01636PD01US 2070
132194 7590 10/04/2021
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (AS)
5005 E. McDowell Road
Maildrop A700
Phoenix, AZ 85008
EXAMINER
REIDA, MOLLY KAY
ART UNIT PAPER NUMBER
2816
NOTIFICATION DATE DELIVERY MODE
10/04/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipdocket@iptech.law
patents@onsemi.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte YUSHENG LIN, ROGER PAUL STOUT,
CHEE HIONG CHEW, SADAMICHI TAKAKUSAKI, and
FRANCIS J. CARNEY
Appeal 2020-006616
Application 15/440,967
Technology Center 2800
Before JEFFREY T. SMITH, JAMES C. HOUSEL, and
N. WHITNEY WILSON, Administrative Patent Judges.
WILSON, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s May 8, 2019 decision to reject claims 1–8 and 21–26 (“Non-
Final Act.”). We have jurisdiction under 35 U.S.C. § 6(b).
We affirm in part.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies the real party in interest as Semiconductor Components Industries, LLC
(Appeal Br. 3).
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Application 15/440,967

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CLAIMED SUBJECT MATTER
Appellant’s disclosure is directed to semiconductor packages. Claim
1, reproduced below from the Claims Appendix, is illustrative of the claimed
subject matter:
1. A semiconductor package, comprising:
a metallic baseplate comprising a first surface and a
second surface opposing the first surface;
a first insulative layer comprising a first surface coupled
to the second surface of the metallic baseplate, the electrically
insulative layer having a second surface opposing the first
surface of the electrically insulative layer;
a first plurality of metallic traces, each metallic trace of
the first plurality of metallic traces coupled to the second
surface of the electrically insulative layer at a first surface of
the metallic trace, each metallic trace of the first plurality of
metallic traces having a second surface opposing the first
surface of the metallic trace;
one or more semiconductor devices comprising a first
surface and a second surface opposing the first surface, wherein
the first surface of the one or more semiconductor devices are
coupled to the second surface of each one of the first plurality
of metallic traces;
a second plurality of metallic traces comprising a first
surface and a second surface, wherein the first surface of at
least one metallic trace of the second plurality of metallic traces
is coupled to the second surface of the one or more
semiconductor devices;
a second insulative layer comprising a first surface
coupled to the second surfaces of the metallic traces of the
upper plurality of metallic traces; and
a mold compound encapsulating the one or more
semiconductor devices;
wherein the semiconductor package is configured to
electrically couple to an external device through external
connectors directly coupled to the first plurality of metallic
traces and not to the second plurality of metallic traces.
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REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Katayose et al. US 6,254,971 B1 July 3, 2001
Hauenstein et al. US 2006/0163648 A1 July 27, 2006
Mochida US 2007/0145540 A1 June 28, 2007
Gao et al. US 9,704,819 B1 July 11, 2017

REJECTIONS
1. Claims 1–6 are rejected under 35 U.S.C. § 102(a)(2) as
anticipated by Gao.
2. Claims 7 and 8 are rejected under 35 U.S.C. § 103 as
unpatentable over Gao in view of Mochida.
3. Claims 21–24 are rejected under 35 U.S.C. § 103 as
unpatentable over Gao in view of Katayose.
4. Claims 25 and 26 are rejected under 35 U.S.C. §103 as
unpatentable over Gao in view of Katayose, and further in view of Mochida.
5. Claims 21–24 are rejected under 35 U.S.C. §103 as
unpatentable over Hauenstein in view of Katayose.
OPINION
Rejection 1 – Anticipation over Gao. “A prior art reference
anticipates a patent claim under 35 U.S.C. § 102(b) if it discloses every
claim limitation.” In re Montgomery, 677 F.3d 1375, 1379 (Fed. Cir. 2012)
(citing Verizon Servs. Corp. v. Cox Fibernet Va., Inc., 602 F.3d 1325, 1336–
37 (Fed. Cir. 2010)). To establish anticipation, every element and limitation
of the claimed invention must be found in a single prior art reference,
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arranged as in the claim. Karsten Mfg. Corp. v. Cleveland Golf Co., 242
F.3d 1376, 1383 (Fed. Cir. 2001).
In this instance, Appellant contends that Gao does not disclose “one or
more semiconductor devices comprising a first surface and a second surface
opposing the first surface, wherein the first surface of the one or more
semiconductor devices are coupled to the second surface of each one of the
first plurality of metallic traces” (Appeal Br. 11, internal citation omitted).
The Examiner finds that this element of claim 1 corresponds to Gao’s
semiconductor devices 130, as illustrated in Gao’s Fig. 1:

Gao FIG. 1 shows a side view of a power electronic package.

The Examiner finds that Gao discloses “one or more semiconductor
devices (130) comprising a first surface and a second surface opposing the
first surface, wherein the first surface of the one or more semiconductor
devices are coupled to the second surface of each one of the first plurality of
metallic traces” (Non-Final Act. 3).
Appellant argues that the claim language requires that the first surface
of the one or more semiconductor devices be coupled to the second surface
of each of the first plurality of metallic traces, and that in Gao’s package, the
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bottom surface of each semiconductor device is only in contact with a single
metallic trace (Appeal Br. 11–13).
The Examiner’s position is that Appellant’s construction of the phrase
“wherein the first surface of the one more semiconductor devices are
coupled to a second surface of each one of the first plurality of metallic
traces” to require that each semiconductor be coupled to each metallic trace
is unfairly narrow (Ans. 3).
It is well established that “the PTO must give claims their broadest
reasonable construction consistent with the specification. . . . Therefore, we
look to the specification to see if it provides a definition for claim terms, but
otherwise apply a broad interpretation.” In re ICON Health & Fitness, Inc.,
496 F.3d 1374, 1379 (Fed. Cir. 2007) (citation omitted). The PTO applies to
the verbiage of the proposed claims the broadest reasonable meaning of the
words in their ordinary usage as they would be understood by one of
ordinary skill in the art, taking into account whatever enlightenment by way
of definitions or otherwise that may be afforded by the written description
contained in the specification. In re Morris, 127 F.3d 1048, 1054 (Fed. Cir.
1997).
The Examiner states that “‘the first plurality of metallic traces’ need
not include all of the traces of [Gao’s] 120A, but can be rightly interpreted to
include only those with semiconductor dies attached to them” (Ans. 3).
Under this interpretation, according to the Examiner, claim 1 reads on Gao’s
structure, though the precise mapping onto the claim is not clearly explained
(Ans. 3–4). However, the Examiner has not presented persuasive reasoning
as to why each of Gao’s traces would not be included in the “first plurality
of metallic traces,” nor has the Examiner explained why single trace 120A
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coupled to semiconductor device 130 may be read to be a first plurality of
traces.
Moreover, according to the Examiner, the claim is properly
interpreted to not require each semiconductor to be coupled to a plurality of
metallic traces because Appellant’s disclosure does not teach its own
semiconductor devices being connected to all traces at the same time (Ans.
4, citing Fig. 31, ¶ 118). Instead the Examiner states that the claim only
requires that “a first surface of each semiconductor device 138 is connected
to a second surface of one of the plurality of traces” (Ans. 4),
notwithstanding the use of the term “each one of” and not “one of” in
connection with the plurality of traces.2
The preponderance of the evidence of record does not support the
Examiner’s position. First, the claim language at issue is plain, stating
explicitly that “the first surface of the one or more semiconductor devices
are coupled to the second surface of each one of the first plurality of metallic
traces.” While the claims are given the broadest reasonable interpretation in
light of the Specification, that interpretation must be consistent with the
claim language. As noted above, the PTO applies the broadest reasonable
meaning of the words in their ordinary usage as they would be understood
by one of ordinary skill in the art. In this case, “each one of the first

2 Appellant directs attention to Specification paragraph 119 for support for
the limitation at issue. Reply Br. 3–4. We note that this paragraph is
directed to the second plurality of traces coupled to second surface of at least
one semiconductor device, not to the first plurality of traces coupled to the
first surface(s) of the semiconductor devices. Whether this paragraph
provides adequate written description for the limitation at issue is not before
us in this appeal. We further note that claim 1, as originally filed, includes
this limitation.
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plurality of metallic traces” plainly means “each one of,” not “one of,” and
requires all of the first plurality of metallic traces.
Accordingly, we reverse the anticipation rejection of claims 1–6 over
Gao.
Rejections 2–4 – Obviousness over Gao in view of Mochida and
Katayose. As discussed above, Appellant has demonstrated reversible error
in connection with the Examiner’s findings regarding Gao’s disclosure.
Each of Rejections 2, 3, and 4 relies on those erroneous findings (see, Non-
Final Act. 5–7). Accordingly, we also reverse each of these rejections.
Rejection 5 – Obviousness of claims 21–24 over Hauenstein and
Katayose. The Examiner’s findings are set forth at page 7–8 of the Non-
Final Action. The Examiner finds that Hauenstein discloses each limitation
of claim 21, except that Hauenstein teaches that its first and second
insulative layers are ceramic instead of laminate, as set forth in claim 21
(Non-Final Act. 8). The Examiner further finds that Katayose teaches that
laminate insulative layers are known in the art, and that it would have been
obvious to substitute in laminate insulative layers for Hauenstein’s ceramic
insulative layers as the obvious selection of a known material based on its
suitability for an intended purpose (id.).
Appellant argues that a person of skill in the art would not have
modified Hauenstein’s structure by using the laminate insulative layer of
Katayose because the process used to produce Hauenstein’s package, which
includes the use of a soldering oven to bond the package, would cause a
laminate to burn up or carbonize (Appeal Br. 17).
Appellant’s argument is not persuasive. The Examiner correctly notes
that the test for obviousness is not whether the features of the secondary
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reference may be bodily incorporated into the primary reference, and finds
that a person of skill in the art would have been able fit the teachings of the
references together (Ans. 4–5). Appellant has argued that “according to the
disclosed process of Hauenstein, the laminate would burn up/carbonize at
the temperatures used in the soldering oven used to bond the package of
Hauenstein, making ceramic a necessary material of the process and device
of Hauenstein” (Appeal Br. 18). However, Appellant has not pointed to—
nor have we found—any specific language in Hauenstein as to what
temperatures would be present in Hauenstein’s soldering oven, much less
that such temperatures would “burn up/carbonize” the laminates disclosed
and/or suggested by Katayose. Moreover, Hauenstein specifically states that
“flexible films” are substitutes for “ceramic substrates” (see, Hauenstein, ¶
7, and claim 24 (“The semiconductor component arrangement of claim 23,
where the substrate is one of a ceramic substrate and a flexible film”).
Thus, on balance, we determine that the preponderance of the
evidence of record does not support Appellant’s argument that a laminate as
taught by Katayose could not be used in Hauenstein’s semiconductor
package. In turn, Appellant has not demonstrated reversible error in the
obviousness rejection of claims 21–24 over Hauenstein in view of Katayose.

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DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–6 102(a)(2) Gao 1–6
7, 8 103 Gao, Mochina 7–8
21–24 103 Gao, Katayose 21–24
25, 26 103 Gao, Katayose,
Mochida
25, 26
21–24 103 Hauenstein, Katayose 21–24
Overall
Outcome
21–24 1–8, 25, 26
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED IN PART