SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Patent Trials and Appeals Board

May 21, 2021

2020003987 (P.T.A.B. May. 21, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/679,666 08/17/2017 Sw WANG ONS02434US 9741
132194 7590 05/21/2021
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (AS)
5005 E. McDowell Road
Maildrop A700
Phoenix, AZ 85008
EXAMINER
GUMEDZOE, PENIEL M
ART UNIT PAPER NUMBER
2899
NOTIFICATION DATE DELIVERY MODE
05/21/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipdocket@iptech.law
patents@onsemi.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte SW WANG, CH CHEW, EIJI KUROSE, and HOW KIAT LIEW
Appeal 2020-003987
Application 15/679,666
Technology Center 2800
Before ADRIENE LEPIANE HANLON, TERRY J. OWENS, and
JULIA HEANEY, Administrative Patent Judges.
HEANEY, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 5–20. See Final Act. 1. We have
jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42. Appellant identifies the real party in interest as Semiconductor
Components Industries. Appeal Br. 3.
Appeal 2020-003987
Application 15/679,666
2
CLAIMED SUBJECT MATTER
The claims are directed to a method for forming semiconductor
packages. Independent claims 5 and 14, reproduced below, are illustrative of
the claimed subject matter:
5. A method for forming semiconductor packages, the method
comprising:
providing a wafer, the wafer comprising a first side and a
second side;
forming a plurality of bumps on the first side of the wafer,
the bumps comprising a first layer and a second layer;
forming one or more grooves between the bumps on the
first side of the wafer, the one or more grooves having a
predetermined depth into the wafer;
overmolding the plurality of bumps with a mold
compound;
grinding the mold compound to expose a face of the
plurality of bumps;
grinding the second side of the wafer to singulate a
plurality of die comprised in overmolding the second side of the
wafer; and
singulating the mold compound between the plurality of
die to form a plurality of semiconductor packages, the plurality
of die fully encapsulated within the mold compound except for
the face of the plurality of bumps.
14. A method for forming semiconductor packages, the method
comprising:
providing a wafer, the wafer comprising a first side and a
second side; forming a first set of bumps on the first side of the
wafer, the first set of bumps comprising a first metal;
forming a second set of bumps on the first set of bumps,
the second set of bumps comprising a second metal different
from the first metal;
sawing one or more grooves between the first set of bumps
and the second set of bumps on the first side of the wafer;
overmolding the first side of the wafer with a mold
compound to encapsulate the first set of bumps and the second
set of bumps;
Appeal 2020-003987
Application 15/679,666
3
grinding the mold compound to expose a face of the
second set of bumps; grinding the second side of the wafer to
singulate a plurality of die comprised in the wafer;
overmolding the second side of the wafer; and
singulating the mold compound between the plurality of
die to form a plurality of semiconductor packages, the plurality
of die being fully encapsulated within the mold compound
except for the face of the second set of bumps. 
REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Okuno US 6,579,748 B1 June 17, 2003
Kato US 2001/0018229 A1 Aug. 30, 2001

REJECTIONS
Claims Rejected 35 U.S.C. § Reference(s)/Basis
5–20 112(a) Written Description
5–20 103 Okuno, Kato

OPINION
Written Description Support
The Examiner finds that there is “no original support and description
for overmolding the second side of the wafer then grinding it to singulate the
wafer” in claims 5 and 14, because the wafer no longer exists after the step
of grinding the wafer to singulate a plurality of die. Final Act. 4–5.
Appellant argues that Figures 2E, 2F, and 2G of the Specification
show that the wafer exists after the step of grinding a second side of the
wafer. Appeal Br. 14. The Appellant argues that the Specification
consistently refers to a “wafer” in steps subsequent to grinding the second
Appeal 2020-003987
Application 15/679,666
4
side, such that a person of ordinary skill in the art would understand that the
wafer exists throughout the steps illustrated in Figures 2E, 2F, and 2G. Id. at
14–15 (citing Spec. ¶¶ 40–41); Reply Br. 3.
We are not persuaded that “overmolding the second side of the
wafer” fails to comply with the written description requirement. The
Specification describes that the wafer exists throughout the steps of forming
the semiconductor package, until the final step when it is singulated into a
plurality of semiconductor packages. See Spec. ¶¶ 38–41; Figs. 2A–2G.
Moreover, the Examiner acknowledges that a wafer still exists after the step
of “grinding the second side of the wafer to singulate a plurality of die
comprised in the wafer.” Answer 5 (stating it was known in the art that “the
combination of the singulated dies and encapsulate 48 is a reconstituted
wafer”). Accordingly, we reverse the rejection.
Obviousness of Claims 5–20
Claim 5
The Examiner finds Okuno discloses a method for forming
semiconductor packages including forming a plurality of bumps, and “the
type of bumps is not particularly limited.” Final Act. 6 (citing Okuno 6:25–
30). The Examiner acknowledges that Okuno does not teach its bumps as
comprising a first and a second layer. Id. The Examiner finds that Kato
teaches forming semiconductor packages having bumps formed of a first
layer of copper and a second layer of gold, or vice-versa. Id. at 6 (citing
Kato ¶ 58, Figs. 5A–B). The Examiner determines it would have been
obvious to a person of ordinary skill in the art to form such bumps to obtain
a reliable joint of solder bumps and a circuit board. Id. at 6–7 (citing Kato
¶¶ 57–58).
Appeal 2020-003987
Application 15/679,666
5
Appellant argues that the rejection fails to establish a prima facie case
because Kato’s intermediate electrode 7, upon which the Examiner relies as
corresponding to a layer of the claimed bump, is inserted between LSI
electrode 2 and solder bump 3. Appeal Br. 20. Appellant argues that Kato
teaches intermediate electrode 7 is an element separate from the solder
bumps. Id.
Appellant’s argument is persuasive of reversible error. Kato explains
that intermediate electrode 7 is inserted between bump 3 and another
element. Kato ¶ 57. In other words, Kato discloses intermediate electrode 7
is a different structure than bump 3, and does not support the Examiner’s
finding that intermediate electrode 7 is a layer of bump 3. Further, the
Examiner’s determination that “the only structural characteristics required
by the claimed bumps is to comprise a first and second layers ...” and Kato’s
bumps “meet those structural characteristics” (Answer 8) is reversible error
because Kato’s bumps are separate structures from its intermediate
electrodes.
Accordingly, we reverse the rejection of claim 5, and claims 6–13
which depend from claim 5.
Claim 14
As with the rejection of claim 5, the Examiner determines that
although Okuno does not disclose the claimed structure of “the first set of
bumps comprising a first metal, forming a second set of bumps on the first
set of bumps, the second bumps comprising a second metal different from
the first metal” (Final Act. 9), it would have been obvious to form first and
second sets of bumps for similar reasons as described in the rejection of
claim 5. Id. at 10.
Appeal 2020-003987
Application 15/679,666
6
We reverse the rejection of claim 14 for the same reasons as discussed
above for claim 5, and we reverse the rejections of claims 15–20 which
depend from claim 14.
CONCLUSION
The Examiner’s rejections are reversed.
DECISION SUMMARY
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
5–20 112(a) Written Description 5–20
5–20 103 Okuno, Kato 5–20
Overall
Outcome
5–20

REVERSED