SanDisk Corporationv.Netlist, Inc.

Patent Trial and Appeal Board

Dec 16, 2014

12761179 (P.T.A.B. Dec. 16, 2014)

Trials@uspto.gov Paper 13
571-272-7822 Entered: March 3, 2015

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

SANDISK CORPORATION,
Petitioner,

v.

NETLIST, INC.,
Patent Owner.

Case IPR2014-01029
Patent 8,516,185 B2

Before LINDA M. GAUDETTE, BRYAN F. MOORE, and
MATTHEW R. CLEMENTS, Administrative Patent Judges.

CLEMENTS, Administrative Patent Judge.

DECISION
Denying Request for Rehearing
37 C.F.R. § 42.71(d)

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I. INTRODUCTION
SanDisk Corporation (“Petitioner”) requests rehearing of the Board’s
decision denying institution of inter partes review of claims 1–19 (“the
challenged claims”) of U.S. Patent No. 8,516,185 B2 (Ex. 1011, “the ’185
patent”) under 35 U.S.C. 103 as obvious over Gower and various other prior
art (Paper 11, “Dec.”), entered December 16, 2014. Paper 12 (“Req.”). For
the reasons that follow, Petitioner’s request is denied.
II. STANDARD OF REVIEW
In its request for rehearing, the dissatisfied party must identify,
specifically, all matters the party believes the Board misapprehended or
overlooked, and the place where each matter was addressed previously.
37 C.F.R. § 42.71(d). Upon a request for rehearing, a decision on institution
will be reviewed for an abuse of discretion. 37 C.F.R. § 42.71(c).
III. DISCUSSION
Petitioner argues that we erred in finding that (1) one of ordinary skill
in the art would not have been motivated to combine Admitted Prior Art
(“APA”) and Gower; (2) Gower fails to disclose transmitting the second set
of module control signals to a plurality of data transmission circuits; and (3)
Leung fails to disclose transmitting the first set of module control signals to
the plurality of sets of memory devices.
A. Motivation to Combine
Petitioner argues that “[t]he Board’s finding is in error because the
subset address transmission feature is not the only improvement of the FIG.
5 embodiment of Gower over the prior art.” Req. 3. According to
Petitioner, “[t]he data line load reduction provided by the data transmission
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circuit of Gower is a wholly separate improvement over the prior art from
the subset address transmission feature. This is evidenced by FIG. 4’s
utilization of a similar data transmission circuit without the subset address
transmission feature.” Pet. 5. Petitioner concludes that, “[b]ecause Gower
describes multiple improvements over the prior art, selection of the data
transmission circuit improvement for data line load reduction without
utilizing one of those improvements (the subset address transmission
feature) does not wholly eviscerate Gower’s improvements over the prior
art.” We are not persuaded by Petitioner’s arguments.
As an initial matter, neither the Petition nor Dr. Neuhauser cited
Figure 4 of Gower as support for the asserted motivation to combine. Pet.
23–24; Ex. 1008 ¶¶ 116, 117. Therefore, we could not have misapprehended
or overlooked it in our Decision to Institute. Moreover, the so-called “data
line load reduction” feature identified by Petitioner is not one of Gower’s
improvements over the prior art; rather, it is the prior art. Petitioner equates
this feature with Figure 4 of Gower. Req. 4 (citing Fig. 4), 5 (“This is
evidenced by FIG. 4’s utilization of a similar data transmission circuit
without the subset address transmission feature.”). Gower, however, clearly
labels this figure as prior art. Figure 4 is reproduced below:

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Ex. 1012, Fig. 4; see also id. at 9:42–59 (describing Figure 4 as using
“known memory system communication protocols.”). Because Gower
describes the configuration depicted in Figure 4 as prior art, we are not
persuaded that we erred in finding that Petitioner’s proposed combination of
Gower and APA would render Gower unsuitable for its intended purpose.
B. Gower
Petitioner argues that we misapprehended the function of Figure 5 of
Gower because “signals 518, 520, and 521 are still sent from memory hub
controller 514 to multiplexers 540, 541, and 550 even in the absence of
address/control signals from the link interface 404 (i.e., when none of the
memory devices 406 associated with that hub device 402 are targeted by the
current operation).” Req. 7 (citing Pet. 17). According to Petitioner,
“[c]ontinued control of multiplexers 540, 541, and 550 is necessary, even
during a wait state for other sets of memory devices to complete operations,
to avoid erroneously outputting incorrect or undefined data on data lines
508.” Id. at 7–8. We are not persuaded by Petitioner’s arguments.
Petitioner concedes that “link interface 404 forwards read or write
commands to the memory hub controller 414 [sic] only if the read or write
command is targeted for memory devices 406.” Req. 7 (emphasis added).
Thus, if the read or write command is not targeted for memory devices 406,
link interface 404 does not forward the read/write command to memory hub
controller 514 which, in turn, does not generate signals 518, 520, and 521
based on that read/write command. Thus, when none of the memory devices
associated with a hub device are targeted by the current read/write operation,
the signals 518, 520, and 521 transmitted from memory hub controller 514
to multiplexers 540, 541, and 550 are not “the second set of module control
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signals” because they are not “generat[ed] . . . based on the address/control
signals” that are “receiv[ed] from the memory controller,” as required by the
preceding steps of claim 13.
C. Leung
Petitioner argues that “[t]he Board appears to interpret the claimed
‘set of memory devices’ to include only the memory arrays (e.g., 402a and
402b) and nothing else. This narrow construction is contrary to the broadest
reasonable interpretation attributable to claim terms in an IPR.” Req. 12.
According to Petitioner, “one of ordinary skill in the art would understand
one of Leung’s memory modules 111-128 to fall within the scope of the
term ‘set of memory devices’” (Req. 10) and “[t]here is no dispute that each
of the memory modules 111-128 receives the claimed first set of module
control signals (e.g., at the control circuitry depicted at the bottom of FIG.
4)” (Req. 12). We are not persuaded by Petitioner’s arguments.
As an initial matter, we are not persuaded that we erred in denying the
asserted ground based on Gower and Leung because we are not persuaded
that we misapprehended Gower, as discussed above. Moreover, with respect
to Leung, Petitioner unambiguously identified the pair of memory arrays
402a, 402b as “a set of two memory devices.” Pet. 28 (“As illustrated in
Figure 4, each memory module 111-128 includes a set of two memory
devices in the form of memory arrays 402a, 402b.”). With respect to
memory modules 111–128, Petitioner argued only that “each include a set of
two memory devices 402a, 402b,” not that each is a set of memory devices.
Id. Accordingly, we are not persuaded that we misapprehended Petitioner’s
argument with respect to Leung.
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IV. CONCLUSION
For the foregoing reasons, the Board did not abuse its discretion when
it denied institution of inter partes review of the challenged claims under
35 U.S.C. § 103 as unpatentable over Gower and various other prior art.

V. ORDER
It is hereby
ORDERED that Petitioner’s request for rehearing is denied.
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For PETITIONER:

David B. Cochran
Joseph M. Sauer
Matthew W. Johnson
JONES DAY
dcochran@jonesday.com
jmsauer@jonesday.com
mwjohnson@jonesday.com

For PATENT OWNER:

Mehran Arjomand
David S. Kim
Erol C. Basol
Jean Nguyen
Jonathan Z. Statman
MORRISON & FOERSTER LLP
marjomand@mofo.com
dkim@mofo.com
ebasol@mofo.com
jnguyen@mofo.com
jstatman@mofo.com