Red Hat Israel, Ltd.

Patent Trials and Appeals Board

Dec 21, 2020

2019004761 (P.T.A.B. Dec. 21, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/034,866 09/24/2013 Michael Tsirkin 08671.295 (L295) 8319
14401 7590 12/21/2020
LOWENSTEIN SANDLER LLP / Red Hat Israel
Patent Docket Administrator
One Lowenstein Drive
Roseland, NJ 07068
EXAMINER
DANG, PHONG H
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
12/21/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents@lowenstein.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte MICHAEL TSIRKIN
____________________

Appeal 2019-004761
Application 14/034,866
Technology Center 2100
____________________

Before JOHNNY A. KUMAR, BETH Z. SHAW, and
JAMES W. DEJMEK, Administrative Patent Judges.

DEJMEK, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1, 8, 14, 15, 26–31, 33–37, 39, and 40. Appellant has canceled
claims 2–7, 9–13, 16–25, 32, 38, and 41. See Appeal Br. 17–20. We have
jurisdiction over the remaining pending claims under 35 U.S.C. § 6(b).
We reverse.

1 Throughout this Decision, we use the word “Appellant” to refer to
“applicant” as defined in 37 C.F.R. § 1.42 (2018). Appellant identifies Red
Hat, Inc. as the real party in interest. Appeal Br. 3.
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STATEMENT OF THE CASE
Introduction
Appellant’s disclosed and claimed invention generally relates to
“managing interrupts generated by network interface controllers.” Spec. ¶ 1.
According to the Specification, in convention systems, a network interface
controller (NIC) may generate an interrupt signal at the completion of
transmitting each packet of data. Spec. ¶ 11. Because each interrupt
requires processing overhead by a CPU to service each interrupt, the claimed
invention seeks to reduce the required processing overhead by reducing the
frequency with which a network interface controller generates interrupts.
Spec. ¶¶ 11–12. In a disclosed embodiment, NIC-generated interrupts
signaling the completion of packet transmission are disabled in response to
determining that a memory pressure metric does not exceed a predetermined
threshold. Spec. ¶¶ 12, 18. In response to determining that the memory
pressure metric exceeds the predetermined threshold, NIC-generated packet
transmission complete interrupts may be enabled. Spec. ¶ 21; see also
Fig. 3. According to the Specification, “the memory pressure metric may
comprise the total size of memory buffers allocated to the transmitted data
packets . . . .[, a] difference between a pre-defined value and the amount of
available physical memory . . . .[, a] number of memory page faults within a
unit of time . . .[, and] a period of time during which an application being
executed by the computer system has been blocked by a memory allocation
operation.” Spec. ¶ 22. In a disclosed and claimed embodiment, disabling
or enabling NIC-generated interrupts is accomplished by writing a pre-
defined value into a configuration register of the NIC. Spec. ¶¶ 18, 21.
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Claim 1 is illustrative of the subject matter on appeal and is
reproduced below:
1. A method, comprising:
responsive to determining, by a processor, that a memory
pressure metric does not exceed a threshold value, writing a first
pre-defined value into an interrupt controller, wherein the
memory pressure metric comprises a period of time during which
an application being executed by a computer system has been
blocked by a memory allocation operation;
responsive to determining that at least a defined number of
data packets have been transmitted by a network interface
controller and that the memory pressure metric exceeds the
threshold value, releasing memory buffers allocated to the data
packets; and
responsive to determining that the memory pressure metric
exceeds the threshold value after releasing the memory buffers,
writing a second pre-defined value into the interrupt controller.

The Examiner’s Rejections2
1. Claims 1, 8, 14, 15, 26–29, 31, 33–35, 37, 39, and 40 stand
rejected under 35 U.S.C. § 103 as being unpatentable over Ma (US
2009/0319733 A1; Dec. 24, 2009); Shimizu (US 2013/0227241 A1;

2 The Examiner had rejected claims 14, 26, 27, 33, 39, and 40 under
35 U.S.C. § 112(b) as being indefinite. Final Act. 2. In response to this
rejection, Appellant amended the claims consistent with the Examiner’s
suggestions. Amdt 2–5 (filed October 22, 2018). In an Advisory Action
(mailed November 6, 2018), the Examiner indicated that the amendments
will be entered for purposes of appeal and that the amendments have
overcome the rejection under 35 U.S.C. § 112(b). See Adv. Act. 1.
Accordingly, we treat the rejection of claims 14, 26, 27, 33, 39, and 40 under
35 U.S.C. § 112(b) as having been withdrawn.
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Application 14/034,866

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Aug. 29, 2013); and Pope et al. (US 2006/0174251 A1; Aug. 3, 2006)
(“Pope”). Final Act. 4–11.
2. Claims 30 and 36 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Ma, Shimizu, Pope, and Srinivasan (US 2010/0205395
A1; Aug. 12, 2010). Final Act. 11–12.

ANALYSIS3
Appellant asserts that Ma, as relied on by the Examiner, fails to teach,
inter alia, responsive to determining that a memory pressure metric does not
exceed a threshold value, writing a first pre-defined value into an interrupt
controller, as recited by claim 1. Appeal Br. 6–10; Reply Br. 3–6. In
particular, Appellant argues Ma teaches “aggregating multiple packets into
one transmit completion interrupt” but does not teach disabling interrupts or,
as recited in the independent claim language, “writing a first pre-defined
value into an interrupt controller” to disable NIC-generated interrupts in
response to a memory pressure metric not exceeding a threshold. Appeal
Br. 6–7 (citing Ma ¶¶ 15, 25, Fig. 3); Reply Br. 3–6. Additionally,
Appellant asserts that Ma does not take any affirmative action (e.g., writing
a pre-defined value into an interrupt controller) if a number of packets
transmitted does not meet a high watermark. Appeal Br. 7–9; Reply Br. 3–4.
Further, Appellant asserts that although Pope teaches disabling interrupts
“by resetting [an] interrupt enable bit,” Pope does not teach that the

3 Throughout this Decision, we have considered the Appeal Brief, filed
January 7, 2019 (“Appeal Br.”); the Reply Brief, filed May 28, 2019 (“Reply
Br.”); the Examiner’s Answer, mailed March 29, 2019 (“Ans.”); and the
Final Office Action, mailed August 23, 2018 (“Final Act.”), from which this
Appeal is taken.
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disabling of interrupts is done in response to determining that a memory
pressure metric does not exceed a threshold value. Appeal Br. 9–10; Reply
Br. 5–6. Moreover, Appellant argues the Examiner relies on impermissible
hindsight in combining the teachings of Ma and Pope because Ma does not
teach taking any affirmative action in response to a number of transmitted
packets not meeting a high watermark (i.e., the claimed memory pressure
metric not exceeding a threshold value) and there would be no reason—
absent Appellant’s Specification—to combine Pope’s disabling of interrupts
by resetting an interrupt enable bit with Ma’s system. Appeal Br. 9.
In rejecting claim 1, the Examiner relies on Figure 3 of Ma and its
accompanying description as teaching “responsive to determining, that a
memory pressure metric does not exceed a threshold value, disabling an
interrupt that signals completion of a packet transmission by a network
interface controller.” Final Act. 4.
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Figure 3 of Ma is illustrative and is reproduced below:

Figure 3 of Ma is a flow chart depicting a disclosed method of
aggregating transmit completion interrupts. Ma ¶ 11.
The Examiner finds that if the number of packets in memory do not
meet a high watermark (i.e., the NO leg of Decision Block (315)), a
completion interrupt is not generated and is, therefore considered as
“disabling interrupts.” Final Act. 4; see also Ans. 3. In support of this
finding, the Examiner explains that Appellant’s Specification “discloses
disabling of interrupt as not generating a completion interrupt (see para
0018), enabling interrupt as generating a completion interrupt (see para
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0021) and further the disabling and enabling of interrupt is performed by
writing pre-defined values into a register of an NIC.” Ans. 3. The Examiner
relies on Pope to teach the details of how to disable/enable interrupt
generation (i.e., by writing a pre-defined value into an interrupt controller).
Final Act. 5–6 (citing Pope ¶ 140).
Appellant responds to the Examiner’s interpretation, and asserts that
the Specification does not describe disabling of interrupts as merely not
generating a completion interrupt, but instead describes an affirmative action
of writing a pre-defined value into a configuration register of a NIC, a local
APIC (Advanced Programmable Interrupt Controller), or an I/O APIC.
Reply Br. 5.
On balance, we find Appellant’s arguments persuasive. As an initial
matter, as identified by the Examiner, Ma does not expressly teach disabling
and enabling interrupts in response to a determination of whether a number
of packets meets a high watermark. Instead, Ma relates to “aggregating
transmit completion interrupts.” Ma ¶¶ 1, 6 (describing the claimed system
can process transmit interrupts “for multiple packets at the same time,
instead of sequentially and/or individually”). Even if we were to accept the
Examiner’s speculative reasoning that because Figure 3 of Ma does not
show generating an interrupt if the number of packets in memory does not
meet a high watermark, and that this is at least suggestive of disabling
interrupts, we note that independent claim 1 (as well as independent claims 8
and 15) does not recite disabling interrupts. Instead, claim 1 recites “writing
a first pre-defined value into an interrupt controller” in response to a
determination that a memory pressure metric does not exceed a threshold
value.
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For us to sustain the Examiner’s rejection, we would need to resort to
impermissible speculation or unfounded assumptions or rationales to cure
the deficiencies in the factual bases of the rejection before us. In re Warner,
379 F.2d 1011, 1017 (CCPA 1967). Moreover, although it is well-
established that any obviousness analysis must, on some level, rely on
hindsight, it is impermissible to engage in a hindsight reconstruction of the
claimed invention, using the Appellant’s invention as a template and
selecting elements from references to fill the gaps. Interconnect Planning
Corp. v. Feil, 774 F.2d 1132, 1143 (Fed. Cir. 1985).
Here, we find the Examiner’s proposed combination of Pope’s writing
a pre-defined value into an interrupt controller to disable interrupt generation
with Ma’s system for aggregating transmit completion interrupts after a
number of packets transmitted meets a high watermark improperly relies on
speculation and hindsight reconstruction. In particular, we find it
speculative that Ma’s disclosed system of aggregating interrupts instead
disables interrupts and transmits only a single interrupt after a high
watermark has been met. Moreover, this speculative reasoning undergirds
the Examiner’s proposed combination of Ma and Pope in order to arrive at a
combination that teaches “responsive to determining, by a processor, that a
memory pressure metric does not exceed a threshold value, writing a first
pre-defined value into an interrupt controller,” as recited in claim 1.
Because we find it dispositive that the Examiner’s proposed
combination of Ma and Pope relies on an impermissible speculation and
hindsight reconstruction of Appellant’s claimed invention, we do not address
other issues raised by Appellant’s arguments related to these claims. See
Beloit Corp. v. Valmet Oy, 742 F.2d 1421, 1423 (Fed. Cir. 1984) (finding an
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administrative agency is at liberty to reach a decision based on “a single
dispositive issue”).
For the reasons discussed supra, we do not sustain the Examiner’s
rejection of independent claim 1. For similar reasons, we do not sustain the
Examiner’s rejection of independent claims 8 and 15, which recite
commensurate limitations. Additionally, we do not sustain the Examiner’s
rejection under 35 U.S.C. § 103 of claims 14, 26–31, 33–37, 39, and 40,
which depend directly or indirectly therefrom.

CONCLUSION
We reverse the Examiner’s decision rejecting claims 1, 8, 14, 15, 26–
31, 33–37, 39, and 40 under 35 U.S.C. § 103.

DECISION SUMMARY
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1, 8, 14, 15,
26–29, 31,
33–35, 37,
39, 40
103 Ma, Shimizu, Pope 1, 8, 14,
15, 26–
29, 31,
33–35,
37, 39, 40
30, 36 103 Ma, Shimizu, Pope,
Srinivasan
30, 36
Overall
Outcome
1, 8, 14,
15, 26–
31, 33–
37, 39, 40

REVERSED