Realtek Semiconductor Corp.

Patent Trials and Appeals Board

May 18, 2021

2020001288 (P.T.A.B. May. 18, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/496,232 04/25/2017 Chi-Kung Kuan 251812-5430 8878
109673 7590 05/18/2021
McClure, Qualey & Rodack, LLP
280 Interstate North Circle SE
Suite 550
Atlanta, GA 30339
EXAMINER
SHYU, JING-YIH
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
05/18/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
dan.mcclure@mqrlaw.com
terri.logan@mqrlaw.com
uspatents@mqrlaw.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
________________

Ex parte CHI-KUNG KUAN and CHIA-LIANG (LEON) LIN
________________

Appeal 2020-001288
Application 15/496,232
Technology Center 2100
________________

Before JASON V. MORGAN, ADAM J. PYONIN, and
MICHAEL J. ENGLE, Administrative Patent Judges.

MORGAN, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–20. We have jurisdiction under 35
U.S.C. § 6(b).
We reverse.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies the real party in interest as Realtek Semiconductor Corporation.
Appeal Br. 2.
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SUMMARY OF THE DISCLOSURE
Appellant’s claimed subject matter relates to a semiconductor die that
includes first and second input/output (I/O) pads, “a switch, and an internal
processor, wherein the switch is configured to short the first I/O pad to the
second I/O pad when a control signal is asserted.” Abstract. An “external
processor is configured to process an electrical signal at the second port in
accordance with a first protocol when the control signal is asserted, and the
internal processor is configured to process an electrical signal at the first I/O
pad when the control signal is de-asserted.” Id.
ILLUSTRATIVE CLAIM
(disputed limitations emphasized and bracketing added)
1. An apparatus comprising:
a semiconductor die including a first I/O (input/output) pad, a
second I/O pad, a switch, and an internal processor, [1] wherein
the switch is configured to selectively short the first I/O pad to
the second I/O pad in response to an on-die control signal
being asserted; and
a semiconductor package including a first bond pad configured
to electrically connect to the first I/O pad, a second bond pad
configured to electrically connect to the second I/O pad, a first
port configured to electrically connect to a high-speed pin of a
multi-mode connector, a second port configured to electrically
connect to an external processor, a first routing path configured
to electrically connect the first port to the first bond pad, and a
second routing path configured to electrically connect the
second port to the second bond pad, [2] wherein the external
processor is configured to process an electrical signal from/to
the second port in accordance with a first protocol when the
control signal is asserted, and the internal processor is
configured to process an electrical signal at the first I/O pad in
accordance with a second protocol when the on-die control
signal is de-asserted.
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REFERENCES
The Examiner relies on the following references:
Name Reference Date
Jao US 2009/0294977 A1 Dec. 3, 2009
Mohanty et al. (“Mohanty”) US 2012/0203937 A1 Aug. 9, 2012
Lee et al. (“Lee”) US 2016/0049876 A1 Feb. 18, 2016
REJECTIONS
The Examiner rejects claims 1–9 and 11–19 under 35 U.S.C. § 103 as
obvious over Jao and Lee. Final Act. 3–10.
The Examiner rejects claims 10 and 20 under 35 U.S.C. § 103 as
obvious over Jao, Lee, and Mohanty. Final Act. 10–11
ANALYSIS
In rejecting claim 1 as obvious, the Examiner finds that the
combination of Jao’s semiconductor die having a plurality of input/output
cells that include bond pads that can be configured and Lee’s synchronous
rectifier teaches or suggests recitation [1], “wherein the switch is configured
to selectively short the first I/O pad to the second I/O pad in response to an
on-die control signal being asserted.” Final Act. 4 (citing Jao ¶¶ 18–24, Figs.
1, 2), 12 (citing Lee ¶¶ 109–10, Figs. 4, 5); Ans. 11. The Examiner finds that
Lee’s synchronous rectifier, which includes a metal oxide semiconductor
field effect transistor (MOSFET), teaches or suggests recitation [2],
“wherein the external processor is configured to process an electrical signal
from/to the second port in accordance with a first protocol when the control
signal is asserted, and the internal processor is configured to process an
electrical signal at the first I/O pad in accordance with a second protocol
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when the on die control signal is de-asserted.” Final Act. 5–6 (citing Lee
¶¶ 109–10, Figs. 4, 5).
Appellant contends the Examiner erred for several reasons. For
example, Appellant argues that the configuration of Jao’s bond pads are
determined by their orientation, not by a selective short. Appeal Br. 7.
Appellant argues “there is no disclosure ANYWHERE in Lee of different
signal protocols.” Id. And Appellant argues both Lee and Jao fail “to
disclose both an internal and an external processor.” Id. Appellant
emphasizes “there is no logical reason to combine Lee with Jao” in the
claimed manner. Reply Br. 2; see also Appeal Br. 10 (“The absence of the
required predictability is evident from the divergent teachings of the
references”).
We agree with Appellant that the Examiner erred. Appellant properly
characterizes Jao, which teaches “controlling an orientation of each bond
pad at the peripheral region of the semiconductor die, thereby selectively
configuring the predetermined connection region thereof to be electrically
connected to one of a plurality of conductive structures included in at least
one metal interconnect layer of the semiconductor die.” Jao, Abstract
(emphasis added); see Appeal Br. 6–7. Thus, Jao does not rely on a switch
selectively shorting bond pads to configure the bonds pads. Moreover, Lee’s
MOSFET does not control the orientation of a bond pad. Rather, Lee uses
the MOSFET as a switch as part of a rectifier (i.e., a device that converts
alternating current into direct current). Lee ¶ 109; see also S. W. Amos, et
al., Newnes Dictionary of Electronics (4th ed.) 267 (1999) (noting that
rectifiers are used in the “process of converting electrical power in the form
of alternating current into unidirectional current”). Thus, the Examiner’s
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findings do not show that Lee’s use of a MOSFET switch teaches or
suggests modifying Jao—which relies on bond pad orientation rather than on
a bond pad short to configure a bond pad—in the claimed manner. Further,
the Examiner’s proffered obviousness reasoning restates the disclosures of
the references, but does not provide a sufficient rationale to modify the
references in the claimed manner. See, e.g., Final Act. 6. Therefore, the
Examiner’s findings do not show that the combination of Jao and Lee
teaches or suggests recitation [1].
Furthermore, as Appellant correctly notes, the Examiner does not
show that Lee teaches both an external and an internal processor (Appeal Br.
7; Reply Br. 3) or that Lee teaches first and second signal protocols (Appeal
Br. 7). Moreover, the Examiner does not show how “various switching
devices [that] can be used in [a] synchronous rectifier to provide a two
channel synchronous rectifier” (Final Act. 6 (citing Lee ¶¶ 109–10)) teaches
or suggests an external and an internal processor. And the Examiner does not
rely on Jao for these teachings. Thus, the Examiner’s findings fail to show
that Lee, alone or in combination with Jao, teaches or suggests recitation [2],
which recites that an “external processor is configured to process an
electrical signal from/to the second port in accordance with a first protocol
when the control signal is asserted” and that an “internal processor is
configured to process an electrical signal at the first I/O pad in accordance
with a second protocol when the on die control signal is de-asserted.”
Accordingly, we do not sustain the Examiner’s 35 U.S.C. § 103
rejection of claim 1, and claims 2–9 and 11–19, which have similar
recitations. The Examiner does not show that Mohanty cures the noted
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deficiencies of Jao and Lee. Therefore, we also do not sustain the
Examiner’s 35 U.S.C. § 103 rejection of claims 10 and 20.
CONCLUSION
In summary:
Claim(s)
Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–9, 11–19 103 Jao, Lee 1–9, 11–19
10, 20 103 Jao, Lee, Mohanty 10, 20
Overall
Outcome
1–20
REVERSED