Rambus Inc.Download PDFPatent Trials and Appeals BoardMay 1, 20202019001429 (P.T.A.B. May. 1, 2020) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/185,793 06/17/2016 Masum Hossain 2016024 / RA1452C1US 1273 78408 7590 05/01/2020 MARC P. SCHUYLER / Rambus P.O. BOX 2535 SARATOGA, CA 95070 EXAMINER SINGH, AMNEET ART UNIT PAPER NUMBER 2633 MAIL DATE DELIVERY MODE 05/01/2020 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte MASUM HOSSAIN and JARED L. ZERBE Appeal 2019-001429 Application 15/185,793 Technology Center 2600 Before JAMES R. HUGHES, JUSTIN BUSCH, and MICHAEL T. CYGAN, Administrative Patent Judges. CYGAN, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 2–4, 7–19, and 21–23, which constitute all the claims pending in this application. Reply Br. 1; Ans. 3 (withdrawing the rejection of claims 5 and 6); Final Act. 27 (claims 20 and 24 objected to as dependent on a rejected claim). Claim 1 has been cancelled. We have jurisdiction under 35 U.S.C. § 6(b). 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest as Rambus Inc. Appeal Br. 1. Appeal 2019–001429 Application 15/185,793 2 We reverse. CLAIMED SUBJECT MATTER A clock and data recovery circuit (a “CDR circuit”) is used in “high speed receivers to recover timing information from an incoming data signal.” Abstract. A clock and data recovery circuit “operates by (1) identifying when there is a logic state transition, and (2) when a logic state transition is identified, voltage is sampled at an expected edge crossing point to determine whether a sampling clock is too early or too late, with the sampling clock responsively being adjusted.” Appeal Br. 2. The claimed invention “relates to a clock and data recovery circuit that has equalization circuitry that equalizes the respective edge and data sampling paths using respective continuous-time linear equalization.” Id. Independent claim 2 is illustrative, with the limitations at issue italicized for emphasis: 2. A clock and data recovery (CDR) circuit to sample an incoming data signal arriving via a conductive signal path, the incoming data signal carrying a sequence of data symbols, the CDR circuit comprising: equalization circuitry to apply first continuous-time linear equalization to the incoming data signal, to obtain an edge path signal, and to apply second continuous-time linear equalization to the incoming data signal, to obtain a data path signal; an edge path sampler to sample the edge path signal at the expected edge crossing times in between adjacent ones of the data symbols in the sequence when said adjacent ones are of reciprocal logic states, to obtain sampled voltages; a data path sampler to sample the data path signal at symbol- sampling times, to recover the data symbols; and circuitry to adjust phase of a recovered clock dependent upon the sampled voltages; wherein the first continuous-time linear equalization and the second continuous-time linear equalization are different. Appeal 2019–001429 Application 15/185,793 3 Independent claims 16 and 21 recite circuits having the above- italicized limitations. Appeal Br. 41–42 (Claims App.). Dependent claims 3, 4, 7–15, 17–19, and 22–23 each incorporate the limitations of their respective independent claims. Appeal Br. 38–43. (Claims App.). The Examiner has withdrawn the rejection of claims 5 and 6. Ans. 3. Claims 20 and 24 are objected to as being dependent on a rejected base claim. Final Act. 27. REFERENCES Name Reference Date Savoj et al. (“Savoj”) “A Wide Common-Mode Fully- Adaptive Multi-Standard 12.5Gb/s Backplane Transceiver in 28 nm CMOS,” 2012 Symposium on VLSI Circuits Digest of Technical Papers 104–05. June 15, 2012 Palmer et al. (“Palmer”) US 2010/0066450 A1 Mar. 18, 2010 Zerbe et al. (“Zerbe ’203”) US 2012/0082203 A1 Apr. 5, 2012 Zerbe et al. (“Zerbe ’043”) US 2006/0188043 A1 Aug. 24, 2006 REJECTIONS Claims 2–4, 9, 10, 14, and 21 are rejected under 35 U.S.C. §103(a) as being obvious over Savoj. Claim 7 is rejected under 35 U.S.C. §103(a) as being obvious over Savoj and Palmer. Claims 8, 11–13, 15, and 22 are rejected under 35 U.S.C. §103(a) as being obvious over Savoj and Zerbe ’203. Appeal 2019–001429 Application 15/185,793 4 Claims 16–18 are rejected under 35 U.S.C. §103(a) as being obvious over Savoj and Appellant’s admitted prior art (AAPA). Claim 19 is rejected under 35 U.S.C. §103(a) as being obvious over Savoj and Zerbe ’043. Claim 23 is rejected under 35 U.S.C. §103(a) as being obvious over Savoj, Zerbe ’203, and AAPA. OPINION Appellant contends error in the Examiner’s rejections, alleging that not all claim limitations are taught by the applied prior art. Appeal Br. 22. Specifically, Appellant points to the limitations of “equalization circuitry to apply first continuous-time linear equalization to the incoming data signal, to obtain an edge path signal, and to apply second continuous-time linear equalization to the incoming data signal, to obtain a data path signal” and “wherein the first continuous-time linear equalization and the second continuous-time linear equalization are different.” Id. Appellant contends that the Examiner errs in finding Savoj to teach or suggest those limitations. Id. With respect to claim 2, the Examiner finds Savoj to teach a clock and data recovery (“CDR”) circuit that obtains an edge path signal with a “low- power AFE path” that applies continuous-time linear equalization (“CTLE”) using AGC and a simplified CTLE to produce an edge path signal through the use of “Crossing signal/information.” Final Act. 5 (citing Savoj 105, Figs. 2 (a), (c)). The Examiner further finds Savoj’s CDR circuit to obtain a data path signal with a “high-loss AFE path” that applies CTLE using AGC and a 3-stage CTLE. Id. The Examiner interprets Savoj as passing an incoming signal having multiple channels through these paths, and selecting Appeal 2019–001429 Application 15/185,793 5 which path individual channels would pass through based upon the loss characteristics of that channel. Ans. 4. The Examiner points to Savoj’s teaching that the outputs of the AFE paths “are merged inside the deserializer.” Ans. 5 (citing Savoj 104) (emphasis omitted). Appellant argues, inter alia, that Savoj’s high-loss and low-power paths do not correspond to the claimed edge and data paths. Appeal Br. 23; Reply Br. 2. Appellant argues that Savoj’s paths are modes used for high loss channels and low-to-moderate loss channels, respectively, that are used in common to produce data and clock samples. Appeal Br. 24; Reply Br. 4. Appellant admits that Savoj’s high-loss and low power paths provide different equalization based upon channel type, but that Savoj’s two AFE paths do not correspond to an edge path producing samples for clock phase adjustment and a differently equalized data path. Appeal Br. 24. We are persuaded by this argument, and therefore do not address Appellant’s additional contentions of error. In order to meet claim 2’s requirement that different CTLEs be applied to the edge signal (which, as claimed, produces a “sampled voltage” used to adjust the phase of a recovered clock) and to the data signal, the Examiner relies upon Savoj’s CTLEs applied to high-loss and low-power AFE paths. Final Act. 5–6. We agree with the Examiner that different CTLEs are applied to the high-loss path and the low-power path. Id. at 6; Savoj 105 (the “high loss-path utilizes . . . a 3-stage continuous-time linear equalizer” and the “low-power path uses . . . simplified CTLE”). The Examiner finds that Savoj’s high-loss and low power paths correspond to the claimed edge and data paths. Id. at 5. The Examiner relates the low-power AFE path to the edge path signal (i.e., the clock path) because it has slicers Appeal 2019–001429 Application 15/185,793 6 that provide crossing data. Id. (citing Savoj 105). However, the high-loss AFE path is also described as having slicers providing crossing data. Savoj 105 (“the high-loss path uses 14 slicers to collect samples on data levels, data crossing”). The Examiner states that Savoj’s “circuitries adjust[] sampling clocks dependent on the sampling signals of the ‘Slicers,’” which are in both the high-loss and low-power paths. Final Act. 6. As interpreted by the Examiner, both paths, although having different CTLEs, appear to produce data used in both data and edge path signals. We do not agree with the Examiner’s reasoning in distinguishing between the high-loss and low-power paths to find the former to teach obtaining the edge path signal and the latter to teach obtaining the data path signal. In contrast, claim 2 requires data and edge signals to be equalized under distinctly different CTLEs. Claim 2 requires that the clock adjustment is dependent on sampled voltages, which are obtained only from the edge path sampler, which is obtained from a first CTLE that must be different from the second CTLE used to produce the data path signal. Although Savoj teaches some of the data path signals and some of the edge path signals are equalized under different CTLE than other data path and edge path signals, Savoj does not teach the particular claimed arrangement set forth in claim 2. To the extent that the Examiner interprets the claim to permit adjusting the clock on sampled voltages that include those obtained from the same CTLE as used to obtain the data path signals, we do not agree that such an interpretation is reasonable. For the above-mentioned reasons, we disagree that Savoj teaches or suggests each and every limitation, arranged as required by claim 2. Accordingly, we reverse the Examiner’s obviousness rejection of claim 2. Appeal 2019–001429 Application 15/185,793 7 Claims 3, 4, 9, 10, 14, and 21 each contain the disputed limitation, and are rejected under the same grounds; therefore, we reverse the Examiner’s rejection of those claims as well. Claims 7, 8, 11–13, 15–19, 22, and 23 each contain the disputed limitation, and are rejected as being obvious over Savoj in view of Palmer, Zerbe ’203, AAPA, and Zerbe ’043, either alone or in various combinations. Final Act. 11–28. The Examiner has not found that the additional references, either alone or in combination, provide the teaching missing from Savoj. Id. Thus, these claims suffer from the same infirmity as claim 2, and we reverse the Examiner’s rejection of claims 7, 8, 11–13, 15–19, 22, and 23 as well. CONCLUSION For the above-described reasons, we reverse the Examiner’s rejection of claims 2–4, 7–19, and 21–23 as being obvious under 35 U.S.C. §103. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § References/Grounds Affirmed Reversed 2–4, 9, 10, 14, 21 103(a) Savoj 2–4, 9, 10, 14, 21 7 103(a) Savoj, Palmer 7 8, 11–13, 15, 22 103(a) Savoj, Zerbe ’203 8, 11–13, 15, 22 16–18 103(a) Savoj, AAPA 16–18 19 103(a) Savoj, Zerbe ’043 19 23 103(a) Savoj, Zerbe ’203, AAPA 23 Overall Outcome 2–4, 7– 19, 21–23 REVERSED Copy with citationCopy as parenthetical citation