Radian Memory Systems, Inc.

Patent Trials and Appeals Board

Aug 27, 2020

2019005230 (P.T.A.B. Aug. 27, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/625,931 06/16/2017 Andrey V. Kuzmin 2016092 / RMS-02C1C1 5329
73091 7590 08/27/2020
Marc P. Schuyler
P.O. Box 2535
Saratoga, CA 95070
EXAMINER
BIRKHIMER, CHRISTOPHER D
ART UNIT PAPER NUMBER
2136
MAIL DATE DELIVERY MODE
08/27/2020 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte ANDREY V. KUZMIN, MIKE JADON, and
RICHARD M. MATHEWS
____________________

Appeal 2019-005230
Application 15/625,9311
Technology Center 2100
____________________

Before MAHSHID D. SAADAT, MARC S. HOFF, and
IRVIN E. BRANCH, Administrative Patent Judges.

HOFF, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 1–25. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
Appellant’s invention is a system and method for cooperation between
host and controller in managing flash memory. The memory controller
maintains information for each erase unit, which assist the host in making
decisions about specific operations, such as garbage collection, space
reclamation, and wear leveling. Abstract. For example, the host receives

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies Radian Memory Systems, Inc. as the
real party in interest. Appeal Br. 1.
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alerts indicative of conditions such as wear, cold data, excessive “released”
space, and low available memory space. The host uses this information in
the scheduling of maintenance operations such that maintenance does not
interfere with writes and reads needed by the host. Spec. ¶ 35. In another
example involving multiple drives, commands from the host can be
interleaved such that, as read and write operations are performed in one
drive, garbage collection and unit erase tasks are performed in another drive.
Spec. ¶ 74.
Claim 1 is exemplary of the claims on appeal:
1. A memory controller integrated circuit to control flash memory, the
flash memory having a plurality of storage locations associated with
structural elements of the flash memory, the memory controller integrated
circuit comprising:
logic to cause said memory controller integrated circuit to detect the
need for operations within the flash memory, said operations comprising one
of
an operation to erase one of the structural elements, and
an operation to move data from one of the storage locations which is
associated with a first one of the structural elements to memory which is
outside of the first one of the structural elements,
wherein upon detection of the need for the one of said operations, said
memory controller integrated circuit is to defer the performance of the one
of said operations, and is to alert a host of the need for the one of said
operations;
logic to transmit to the host information identifying the need for the
one of said operations;
logic to receive at least one of read requests and write requests from
the host and to control the performance of the at least one of the read
requests and the write requests, notwithstanding prior transmission to the
host of said information and notwithstanding the pending need for the one of
said operations; and
logic to receive a command from the host, interleaved amongst the at
least one of the read requests and the write requests, to perform the one of
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said operations, and to responsively control the performance of the one of
said operations;
wherein each said logic comprises at least one of (1) hardware circuit
elements or (2) instructions stored on non-transitory storage which, when
executed, are to control circuitry of said memory controller integrated
circuit; and
wherein timing of the command from the host to perform the one of
said operations is effective to determine when the memory controller
integrated circuit is to perform the one of said operations, relative to
performance of the at least one of the read requests and the write requests.

The Examiner relies upon the following prior art in rejecting the
claims on appeal:
Merry US 2007/0260811 A1 Nov. 8, 2007

Claims 1–25 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Merry.
Throughout this Decision, we make reference to the Appeal Brief
(“Appeal Br.,” filed Feb. 13, 2019), the Reply Brief (“Reply Br.,” filed June
24, 2019), and the Examiner’s Answer (“Ans.,” mailed Apr. 24, 2019) for
their respective details.

ISSUE
Appellant’s arguments present us with the following issue:
1. Does Merry teach logic to cause a memory controller to, upon
detection of the need for an operation to erase one of the structural elements
or to move data to memory outside one of the structural elements, defer the
performance of the operation and alert a host of the need for the operation?
2. Does Merry teach receiving a command from the host, interleaved
amongst the at least one of the read requests and the write requests, to
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perform the move operation or erase operation, and to responsively control
the performance of the move operation or erase operation?

PRINCIPLES OF LAW
“A rejection for anticipation under section 102 requires that each and
every limitation of the claimed invention be disclosed in a single prior art
reference.” See In re Buszard, 504 F.3d 1364, 1366 (Fed. Cir. 2007)
(quoting In re Paulsen, 30 F.3d 1475, 1478–79 (Fed. Cir. 1994)).
Anticipation of a claim requires a finding that the claim at issue reads on a
prior art reference. Atlas Powder Co. v. IRECO, Inc., 190 F.3d 1342, 1346
(Fed. Cir. 1999) (quoting Titanium Metals Corp. v. Banner, 778 F.2d 775,
781 (Fed. Cir. 1985)).

ANALYSIS
We select claim 1 as representative of the claims under appeal,
pursuant to our authority under 37 C.F.R. § 41.37(c)(1)(vii).
Independent claim 1 recites, inter alia, logic to detect the need for operations
(such as erasing a structural element, or moving data from one storage
location to memory outside of the first structural element) within flash
memory, whereupon detection of the need for such an operation, the
memory controller integrated circuit is to defer the performance of said
operation, and is to alert the host of the need for the operation.
Independent claim 1 further recites, inter alia, logic to receive a
command from the host, interleaved amongst the at least one of read
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requests and write requests, to perform the one of said operations, and to
responsively control the performance of the one of said operations.
The Examiner finds that Merry teaches the claimed deferral of
performance of a move or erase operation. Ans. 14. The Examiner finds that
Merry teaches a controller that performs the analysis of the count data
including when wear level is to be performed. Id.; Merry ¶¶ 47, 52. The
result of the analysis is sent to the host and the host uses a driver and/or
storage manager to send wear leveling commands to the host. Id.
We have reviewed Merry, and we find that Merry does not teach a
controller that “defer[s] the performance of the one of said operations,” as is
claimed. See Reply Br. 1–2. Merry’s system reports information to a host
system that uses the information to measure or determine the useful life
remaining in non-volatile storage components. Merry ¶ 7. Merry teaches
analyzing raw data from controller 114 to determine the amount of life left
in nonvolatile memory array 116. Merry ¶ 47. In the other paragraph cited
by the Examiner, Merry teaches wear leveling, generally, in a system with
“two solid-state storage subsystems.” Merry ¶ 52. The Examiner fails to
identify any specific teaching of “deferral” in Merry, and we find that Merry
does not teach deferring a move or erase operation as is claimed.
The Examiner further finds that Merry teaches logic to receive a
command from the host, interleaved amongst the at least one of the read
requests and write requests, to perform the one of said operations [i.e., move,
erase], and to responsively control the performance of the one of said
operations. Ans. 16. The Examiner cites to paragraph 42, which generally
discloses wear leveling, “used to map the same logical data to different
physical locations.” Merry ¶ 42. “When the number of spare data blocks 404
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falls below a selected threshold, the controller 114 may, in some
embodiments, be configured to interrupt and sent a notification message to
the host system 110.” Id.
We do not agree with the Examiner that this passage in Merry teaches
the claimed interleaved receipt of commands and responsive control of
performance. The word “interrupt” appears precisely once in Merry, at the
quoted location in paragraph 42. All that is taught by Merry there is a
“notification” to the host system of a low number of spare data blocks. We
find that Merry does not teach the interleaved receipt of move or erase
commands, among read commands and write commands, from the host, as
the claim requires. Further, we have reviewed Merry and we find no support
for the Examiner’s statement that paragraphs 42 and 52 together disclose
that controller 114 causes “the host 110 to interrupt any current reading or
writing processes and interleave a wear leveling process into the hosts 110
execution (sic).” Ans. 16.
We find, as a result, that Merry does not teach all of the elements of
representative claim 1. We do not sustain the Examiner’s § 102(b) rejection
of claims 1–25 over Merry.

CONCLUSION
1. Merry does not teach logic to cause a memory controller to, upon
detection of the need for an operation to erase one of the structural elements
or to move data to memory outside one of the structural elements, defer the
performance of the operation and alert a host of the need for the operation.
2. Merry does not teach receiving a command from the host,
interleaved amongst the at least one of the read requests and the write
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requests, to perform the move operation or erase operation, and to
responsively control the performance of the move operation or erase
operation.
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/
Basis
Affirmed Reversed
1–25 102(b) Merry 1–25
Overall
Outcome

1–25

ORDER
The Examiner’s decision to reject claims 1–25 is reversed.

REVERSED