QUALCOMM INCORPORATED

Patent Trials and Appeals Board

Jan 29, 2021

2020000457 (P.T.A.B. Jan. 29, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/173,251 06/03/2016 Michael A. Stuber 36340.354US16_54214 1759
101306 7590 01/29/2021
Haynes and Boone, LLP (36340)
IP Section
2323 Victory Avenue, Suite 700
Dallas, TX 75219
EXAMINER
HUYNH, ANDY
ART UNIT PAPER NUMBER
2818
NOTIFICATION DATE DELIVERY MODE
01/29/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
gary.edwards@haynesboone.com
ipdocketing@haynesboone.com
ocpat_uspto@qualcomm.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL A. STUBER, STUART B. MOLIN,
MARK DRUCKER, and PETER FOWLER
Appeal 2020-000457
Application 15/173,251
Technology Center 2800
Before JEFFREY T. SMITH, JEFFREY B. ROBERTSON, and
JAMES C. HOUSEL, Administrative Patent Judges.
SMITH, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–20. See Final Act. 1. We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 We use the term “Appellant” to refer to “applicant” as defined in 37 C.F.R.
§ 1.42. Appellant identifies the real party in interest as Qualcomm Inc.
(Appeal Br. 3.)
Appeal 2020-000457
Application 15/173,251
2
CLAIMED SUBJECT MATTER
The claims are directed to an integrated circuit assembly including a
semiconductor-on-insulator (SOI) coupled to the second (back) surface of a
substrate and where the substrate has an active layer formed on a first (front)
surface. Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. An integrated circuit assembly comprising:
a silicon on insulator (SOI) insulating layer having a first
surface and a second surface;
a first active layer contacting the first surface of the SOI
insulating layer;
a metal bond pad formed on the second surface of the SOI
insulating layer;
wherein the metal bond pad is electrically coupled to the
first active layer;
a substrate having a first surface and a second surface, the
first active layer being coupled to the second surface of the
substrate;
a second active layer formed on the first surface of the
substrate;
a first singulated wafer portion including the SOI
insulating layer and the first active layer; and
a second singulated wafer portion bonded to the first
singulated wafer portion, the second singulated wafer portion
including the substrate and the second active layer, wherein a
back side of the second singulated wafer portion is bonded to a
top side of the first singulated wafer portion, and wherein an
additional metal bond pad is disposed on a front side of the
second singulated wafer portion.
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Application 15/173,251
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REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Belleville US 2002/0094629 A1 July 18, 2002
Kweon US 2007/0262436 A1 Nov. 15, 2007
Bernstein US 2008/0165521 A1 July 10, 2008

REJECTIONS
I. Claims 1–9 and 11–20 are rejected under 35 U.S.C. § 103(a) as
unpatentable over the combination of Kweon and Belleville. (Final Act. 4.)
II. Claim 10 is rejected under 35 U.S.C. § 103(a) as unpatentable over
the combination of Kweon, Belleville, and Bernstein. (Final Act. 9.)
OPINION
We review the appealed rejections for error based upon the issues
Appellant identifies, and in light of the arguments and evidence produced
thereon. See In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011) (“[I]t has long
been the Board’s practice to require an applicant to identify the alleged error
in the examiner’s rejections,” citing Ex parte Frye, 94 USPQ2d 1072, 1075
(BPAI 2010) (precedential)).
Claims 1–9 and 11–20 are rejected under 35 U.S.C. § 103(a) as
unpatentable over the combination of Kweon and Belleville.
Our analysis applies to independent claims 1 and 11. While Appellant
presents arguments under the headings “Claims 1–9,” “Claims 11–15,” and
“Claims 16–20,” Appellant only presents substantive arguments addressing
independent claim 1. (Appeal Br. 7–14). We limit our discussion to
independent claim 1 as argued by Appellant.
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Application 15/173,251
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The Examiner finds Kweon discloses an integrated circuit assembly
that suggests the structure required by the claimed invention. (Final
Act. 4–5; Kweon Figure 3, ¶¶ 29–42.) The Examiner finds Kweon differs
from the claimed invention by failing to disclose the integrated circuit
assembly comprising a silicon on insulator (SOI) insulating layer. (Final
Act. 5.) The Examiner finds Belleville discloses that making integrated
circuits on SOI type substrates can increase the integration density, reduce
parasite capacitances and improve performances of circuits in terms of
operating frequency and consumption. (Final Act. 5; Belleville ¶19). The
Examiner concludes it would have been obvious to utilize integrated circuits
on SOI type substrates, such as taught by Belleville, to form a silicon on
insulator (SOI) insulating layer in Kweon to arrive at the claimed invention.
(Final Act. 5.)
Appellant argues Kweon does not teach a back side of the second
singulated wafer portion is bonded to a top side of the first singulated wafer
portion. (Appeal Br. 9.)
Appellant’s arguments are not persuasive of reversible error.
Kweon teaches several embodiments of microelectronic devices and
methods for manufacturing microelectronic devices including attaching a
plurality of singulated microelectric devices. (Kweon ¶ 22.) Kweon teaches
embodiments describing stacked microelectronic devices that provide the
advantages of increasing the capacity and/or performance of a device within
a given surface area on a circuit board. (Kweon ¶ 41.) Kweon teaches the
stacked microelectronic devices can have a variety of arrangements as
depicted in Figures 3–7. These depictions include arrangements wherein the
singulated microelectric devices are attached in a front to back arrangement.
Thus, a person having ordinary skill in the art would have drawn a
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reasonable inference from Kweon’s teachings for the formation of singulated
microelectric devices that are attached in a front to back arrangement. See In
re Preda, 401 F.2d 825, 826 (CCPA 1968) (“[I]n considering the disclosure
of a reference, it is proper to take into account not only specific teachings of
the reference but also the inferences which one skilled in the art would
reasonably be expected to draw therefrom.”);
Appellant argues Belleville teaches away from the proposed
combination with Kweon because Belleville teaches a more complex SOI
structure that would not accommodate a metal bond pad formed on its
surface. (Appeal Br. 11.)
Appellant’s argument is not well taken because the state of the art as a
whole indicates connecting stacked adjacent microelectronic devices through
intervening layers was known to persons of ordinary skill in the art.
Assuming Appellant is correct that Belleville teaches a more complex
SOI structure, this disclosure does not teach away from a structure that may
be considered inferior. “A reference does not teach away, however, if it
merely expresses a general preference for an alternative invention but does
not ‘criticize, discredit, or otherwise discourage’ investigation into the
invention claimed.” DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc.,
567 F.3d 1314, 1327 (Fed. Cir. 2009) (citing In re Fulton, 391 F.3d 1195,
1201 (Fed. Cir. 2004)); see also In re Dunn, 349 F.2d 433, 438 (CCPA
1965). Kweon teaches it was known to connect stacked microelectronic
devices utilizing adjacent bonding surfaces through an intervening underfill
layer 372. (Kweon Fig. 5). Belleville teaches the advantages of utilizing a
separating insulator layer were known to persons of ordinary skill in the art.
(Belleville ¶ 19.) A person of ordinary skill in the art would have reasonably
expected that utilizing an insulating layer between Kweon’s adjacent
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Application 15/173,251
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microelectronic devices would have achieved the advantages described by
Belleville. “If a person of ordinary skill can implement a predictable
variation, § 103 likely bars its patentability. For the same reason, if a
technique has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar devices in the
same way, using the technique is obvious unless its actual application is
beyond his or her skill.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417
(2007).
Based on the foregoing, we sustain the Examiner’s obviousness
rejection of claims 1–9 and 11–20. We likewise affirm the Examiner’s
decision to reject dependent claim 10. The Examiner’s additional reliance on
Bernstein for the rejection of dependent claim 10 was not separately argued
by Appellant.

DECISION SUMMARY
Claim(s)
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–9, 11–20 103(a) Kweon, Belleville 1–9, 11–20
10 103(a) Kweon, Belleville,
Bernstein
10
Overall
Outcome
1–20

RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED