QUALCOMM Incorporated

Patent Trials and Appeals Board

Mar 28, 2022

2021000365 (P.T.A.B. Mar. 28, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/192,992 06/24/2016 Eric Wayne MAHURIN QC161368 7249 12371 7590 03/28/2022 Muncy, Geissler, Olds & Lowe, P.C./QUALCOMM 4000 Legato Road, Suite 310 Fairfax, VA 22033 EXAMINER ALLI, KASIM A ART UNIT PAPER NUMBER 2183 NOTIFICATION DATE DELIVERY MODE 03/28/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): meo.docket@mg-ip.com meo@mg-ip.com ocpat_uspto@qualcomm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ERIC WAYNE MAHURIN, JAKUB PAWAL GOLAB, and LUCIAN CODRESCU Appeal 2021-000365 Application 15/192,992 Technology Center 2100 Before ST. JOHN COURTENAY III, ELENI MANTIS MERCADER, and ERIC S. FRAHM, Administrative Patent Judges. MANTIS MERCADER, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 9, 12, 13, 20, and 23. Claims 1-8, 10, 11, 14-19, 21, and 22 are canceled. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM. 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a) (2012). Appellant identifies the real party in interest as QUALCOMM Incorporated. Appeal Br. 3. Appeal 2021-000365 Application 15/192,992 2 CLAIMED SUBJECT MATTER The claims are directed to performing a memory operation wherein two or more source addresses and two or more destination addresses are non-contiguous. See Spec. para. 30. Claim 9, reproduced below, is illustrative of the claimed subject matter: 9. A method of performing a memory operation, the method comprising: providing, by a processor, two or more source addresses and corresponding two or more destination addresses of a memory, wherein the two or more source addresses are orthogonal or independent and non-contiguous with one or more data elements at one or more other source addresses arranged between two or more data elements at the two or more source addresses, and wherein the two or more destination addresses are orthogonal and non-contiguous or independent and non- contiguous in the memory, and wherein the two or more source addresses are different than the two or more destination addresses; and executing two or more instructions for copying the two or more data elements from the two or more source addresses to the corresponding two or more destination addresses within the memory, without an intermediate copy to a register in the processor. Appeal 2021-000365 Application 15/192,992 3 REFERENCE The prior art relied upon by the Examiner is: Name Reference Date Fleischer US 2014/0136811 A1 May 15, 2014 REJECTIONS2 Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis 9, 12, 13, 20, 23 112(a) Written Description 9, 12, 13, 20, 23 102(a) Fleischer OPINION 1. Claims 9, 12, 13, 20, and 23 rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The Examiner finds that there is no description in the Specification of the source addresses being different from the destination addresses as required by independent claims 9 and 20. See Final Act. 7-8. The Examiner notes that while the Specification discloses source addresses and corresponding destination addresses, this is not enough to support the more specific detail that the source addresses are different from the destination addresses. Id. Appellant has not responded to the Examiner’s rejection. See Appeal Br. 2 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125 Stat. 284 (2011), amended 35 U.S.C. §§ 102 and 112. Because the present application has an effective filing date of June 24, 2016, after to the AIA’s effective date (March 16, 2013), this decision refers to the post-AIA 35 U.S.C. §§ 102 and 112 statutes. Appeal 2021-000365 Application 15/192,992 4 Accordingly, we summarily affirm the Examiner’s Rejection of claims 9, 12, 13, 20, and 23 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. 2. Claims 9, 12, 13, 20, and 23 rejected under 35 U.S.C. 102(a) as anticipated by Fleischer. The Examiner finds that Fleischer in paragraph 43 discloses the limitation “wherein the two or more destination addresses are orthogonal and non-contiguous or independent and non-contiguous in the memory.” Final Act. 9 (citing para. 43, emphasis added). The Examiner finds that the list 510 specifies a vector of stride sizes associated with each destination address increment where the strided addresses, i.e. the destination addresses plus offsets, are independent in the memory since the offsets are able to be specified independently for each data element, and are non-contiguous since a vector of different stride sizes ensures that some destination addresses will be strided over/skipped in the stride resulting in non-contiguous destination addresses. Id. Appellant argues that contrary to the Examiner’s finding, Figure 5, which the Examiner relies on, shows a scenario where there is scattered data (non-contiguous) that is retrieved and then stored in a non- scattered/consolidated configuration (contiguous). Appeal Br. 5 (citing Fig. 5). Appellant points us to the explicit disclosure regarding Fleischer’s Figure 5 stating Appeal 2021-000365 Application 15/192,992 5 data elements A, B, C, and D are located in noncontiguous memory locations, where data elements B and D are in memory vault 502 while data elements A and C are in memory vault 504. In response to the gather instruction, the processing element reads data elements A, B, C, and D from various locations in memory vaults 502 and 504 and writes data elements A, B, C, D into contiguous locations 506 in a memory region 508 that is accessible by the main processor which issued the gather instruction. See Reply Br. 3 (citing Fleisher, para. 42). Furthermore, Appellant argues that Fleischer’s statement at paragraph 47 which states that “[t]he stride size can be a single value for all data elements or can be a vector to support different stride sizes associated with each source address increment,” means that the stride size refers to the size of a particular data element indexed at a particular source address, i.e., the number of bits stored at each source address.3 Appeal Br. 9 (emphasis added and omitted). The stride size would most likely be defined in terms of a bit-length or bytelength, so a stride size=1 is not a particularly reasonable example. Id. Appellant argues that an interpretation of paragraph 47 of Fleischer’s statement that “a source address from which to read contiguous memory locations 602” is only true for a stride size of 1 is not particularly reasonable. Id. Appellant believes that a more reasonable interpretation of Fleischer’s teachings is as follows: 3 Paragraph 43 regarding Figure 5, as opposed to paragraph 47 regarding Figure 6, also recites the same language. See Fleischer’s paras. 43, 47. Appeal 2021-000365 Application 15/192,992 6 Appellant argues that the stride size can be scaled without the successive source addresses from which data elements are read becoming non-contiguous. Id. We find a preponderance of the evidence supports Appellant’s argument, because Fleischer explicitly discloses with respect to Figure 5, “that the processing element reads data elements A, B, C, and D from various locations in memory vaults 502 and 504 and writes data elements A, B, C, D into contiguous locations 506 in a memory region 508.” See Fleischer, para. 42 (emphasis added). This is further illustrated in Figure 5 reproduced below: Appeal 2021-000365 Application 15/192,992 7 Figure 5 shows data elements A, B, C, and D located in non- contiguous memory locations, where data elements B and D are in memory vault 502 while data elements A and C are in memory vault 504, and in response to the gather instruction, the processing element reads data elements A, B, C, and D from various locations in memory vaults 502 and 504 and writes data elements A, B, C, D into contiguous locations 506. See Fleisher, para. 42. Appeal 2021-000365 Application 15/192,992 8 Furthermore, the Examiner’s finding that the stride sizes associated with each destination address increment where the strided addresses, i.e. the destination addresses plus offsets, are independent in the memory since the offsets are able to be specified independently for each data element, and are non-contiguous since a vector of different stride sizes ensures that some destination addresses will be strided over/skipped in the stride resulting in non-contiguous destination addresses, is not supported by the record before us. See Final Act. 9 (citing Fleischer, para. 43). Paragraphs 42 and 43 disclose the embodiment of Figure 5 which explicitly describe writing data elements A, B, C, D (i.e., destination addresses) into contiguous locations 506. See Fleischer, paras. 42, 43. “It is well settled that a prior art reference may anticipate when the claim limitations not expressly found in that reference are nonetheless inherent in it. Under the principles of inherency, if the prior art necessarily functions in accordance with, or includes, the claimed limitations, it anticipates.” In re Cruciferous Sprout Litig., 301 F.3d 1343, 1349 (Fed. Cir. 2002) (citations and internal quotation marks omitted). “Inherency, however, may not be established by probabilities or possibilities. But the mere fact that a certain thing may result from a given set of circumstances is not sufficient.” In re Robertson, 169 F.3d 743, 745 (Fed. Cir. 1999) (citations and internal quotation marks omitted). Accordingly, with respect to the Examiner’s findings regarding the probable or possible interpretation of “stride” and its inference of teaching non-contiguous destination addresses is not appropriate under anticipation. See Robertson at 745. Accordingly, we reverse the Examiner’s rejection of claims 9, 12, 13, 20, and 23 rejected under 35 U.S.C. 102(a) as anticipated by Fleischer. Appeal 2021-000365 Application 15/192,992 9 CONCLUSION The Examiner’s (i) written description rejection of claims 9, 12, 13, 20, and 23 is affirmed; and (ii) anticipation rejection of claims 9, 12, 13, 20, and 23 is reversed. Because we have affirmed at least one ground of rejection with respect to each claim on appeal, the Examiner’s decision is affirmed. See 37 C.F.R. § 41.50(a)(1). DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 9, 12, 13, 20, 23 112(a) Written Description 9, 12, 13, 20, 23 9, 12, 13, 20, 23 102(a) Fleischer 9, 12, 13, 20, 23 Overall Outcome 9, 12, 13, 20, 23 TIME PERIOD FOR RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv) (2013). AFFIRMED