Phua, Yoke Hor et al.

Patent Trials and Appeals Board

Sep 4, 2019

13937952 - (D) (P.T.A.B. Sep. 4, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/937,952 07/09/2013 Yoke Hor Phua 2515.0371 CON 1063
112165 7590 09/04/2019
STATS ChipPAC/PATENT LAW GROUP:
Atkins and Associates, P.C.
123 West Chandler Heights Road, Unit 12535
Chandler, AZ 85248
EXAMINER
CHANG, JAY C
ART UNIT PAPER NUMBER
2895
NOTIFICATION DATE DELIVERY MODE
09/04/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
main@plgaz.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte YOKE HOR PHUA
and YUNG KUAN HSIAO1
____________

Appeal 2019-000818
Application 13/937,952
Technology Center 2800
____________

Before BEVERLY A. FRANKLIN, GEORGE C. BEST, and
MERRELL C. CASHION, JR., Administrative Patent Judges.

FRANKLIN, Administrative Patent Judge.

DECISION ON APPEAL

Appellant requests our review under 35 U.S.C. § 134(a) of the
Examiner’s decision finally rejecting claims 14–17 and 20–31. We have
jurisdiction over the appeal under 35 U.S.C. § 6(b).
We affirm.

1 STATS ChipPAC Pte. Ltd. is the Applicant/Appellant and is identified as
the real party in interest. App. Br. 1.
Appeal 2019-000818
Application 13/937,952

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STATEMENT OF THE CASE
Claim 14 is illustrative of Appellant’s subject matter on appeal and is
set forth below:
14. A semiconductor device, comprising:
semiconductor wafer including a plurality of first
semiconductor die arranged across an entire surface area of the
semiconductor wafer to yield a first number of the first
semiconductor die disposed on the semiconductor wafer given
the surface area of the semiconductor wafer;
a reconstituted wafer including a plurality of second
semiconductor die arranged across an entire surface area of the
reconstituted wafer to yield a second number of the second
semiconductor die disposed in contact with the reconstituted
wafer given the surface area of the reconstituted wafer, wherein
the surface area of the reconstituted wafer is greater than the
surface area of the semiconductor wafer, and a footprint of the
first semiconductor die is equal to a footprint of the second
semiconductor die, and
the second number of the second semiconductor die
arranged across the surface area of the reconstituted wafer is
greater than the first number of the first semiconductor die
arranged across the surface area of the semiconductor wafer;
an encapsulant disposed over the reconstituted wafer
between the second semiconductor die, wherein a surface of the
encapsulant between the second semiconductor die is coplanar
with a surface of the second semiconductor die; and
an interconnect structure formed over the second
semiconductor die and encapsulant opposite the reconstituted
wafer.
Appeal 2019-000818
Application 13/937,952

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THE REJECTIONS2
1. Claims 14–17 and 20–31 are rejected under 35 U.S.C. § 112(a) or 35
U.S.C. § 112 (pre-AIA), first paragraph, as failing to comply with the
written description requirement.
2. Claims 14–17 and 20–31 are rejected under 35 U.S.C. § 112(b) or 35
U.S.C. § 112 (pre-AIA), second paragraph, as indefinite.
ANALYSIS
For purposes of this appeal, we address separately argued claim 14
and the remaining claims stand or fall with claim 14, consistent with 37
C.F.R. § 41.37(c)(1)(iv) (2017).
Upon consideration of the evidence and each of the respective
positions set forth in the record, we find that the preponderance of evidence
supports the Examiner’s findings and conclusions. Accordingly, we sustain
each of the Examiner’s rejections on appeal essentially for the reasons set
forth in the Final Office Action and in the Answer, and affirm, with the
following emphasis.
Rejection 1
It is the Examiner’s position that there is no written description
support for a semiconductor device having both a semiconductor wafer and a

2 Beginning on page 6 of the Final Office Action, the Examiner objects to
the Drawings. Appellant discusses this objection on page 5 of the Appeal
Brief. The Examiner’s objection to the drawings is reviewable by petition
under 37 C.F.R. § 1.181 and is thus not within the jurisdiction of the
Board. 37 C.F.R. § 1.127 (2009); In re Berger, 279 F.3d 975, 984 (Fed.
Cir. 2002) (citing In re Hengehold, 440 F.2d 1395, 1403–04 (CCPA
1971)).
Appeal 2019-000818
Application 13/937,952

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reconstituted wafer. The Examiner’s rejection is set forth on pages 9–13 of
the Final Office Action.
Appellant’s position is set forth on pages 6–11 of the Appeal Brief,
(which includes reference to Mr. Kuan Heap Hoe’s Rule 132 Declaration),
and on pages 1–4 of the Reply Brief. While we appreciate Appellant’s
position expressed therein of the association of a semiconductor wafer and a
reconstituted wafer in coexistence, in a semiconductor manufacturing line,
we agree with the Examiner that there is insufficient support of a
semiconductor device having both a semiconductor wafer and a
reconstituted wafer. A manufacturing line (or “working fab” as mentioned
on page 3 of the Declaration) differs from a semiconductor device, and we
are unpersuaded that the plain meaning of “semiconductor device” is
sufficiently broad to encompass such an association of a semiconductor
wafer and a reconstituted wafer.
In view of the above, we affirm Rejection 1.
Rejection 2
We also affirm Rejection 2 for reasons similar to those expressed
above with respect to Rejection 1. That is, we agree with the Examiner for
the reasons provided in the record that claim 14 is indefinite because it
recites a device having both a semiconductor wafer and a reconstituted
wafer.3
In view of the above, we affirm Rejection 2.

3 With regard to the phrase involving the die being “arranged across an
entire surface area of the semiconductor wafer”, we agree with Appellant
that this phrase is definite in light of the Specification and its plain meaning.
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Application 13/937,952

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DECISION
Each rejection is affirmed.
TIME PERIOD
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED