Perego et al.v.Drehmel et al.

Board of Patent Appeals and Interferences

Jun 24, 2010

11203652 (B.P.A.I. Jun. 24, 2010)

BoxInterferences@uspto.gov Paper 155 1
Telephone: 571-272-4683 Entered: 24 June 2010 2
3
UNITED STATES PATENT AND TRADEMARK OFFICE 4
5 6
7
BEFORE THE BOARD OF PATENT APPEALS 8
AND INTERFERENCES 9
10 11
12
RICHARD E. PEREGO, STEFANOS SIDIROPOULOS 13
and ELY TSERN 14
Junior Party 15
(Patent 6,502,161) 16
17
v. 18
19
ROBERT ALLEN DREHMEL, KENT HAROLD HASELHORST, 20
RUSSELL DEAN HOOVER and JAMES ANTHONY MARCELLA 21
Senior Party 22
(Application 11/203,652) 23
24 25
26
Patent Interference No. 105,467 (JL) 27
(Technology Center 2100) 28
29 30
31
Before: RICHARD E. SCHAFER, JAMESON LEE, and RICHARD 32
TORCZON, Administrative Patent Judges. 33
34
LEE, Administrative Patent Judge. 35
36
DECISION ON PRIORITY 37
Interference No. 105,467
Perego v. Drehmel

2
A. Introduction 1
The interference is before a merits panel of the Board for a decision 2
on the question of priority. Both parties filed a motion for priority of 3
invention -- Perego’s Motion 9 and Drehmel’s Motion 1. Drehmel has also 4
filed Miscellaneous Motion 2 to exclude a multitude of Perego exhibits. 5
B. General findings of fact 6
The junior party is named inventors Richard E. Perego, Stefanos 7
Sidiropoulos, and Ely Tsern (collectively “Perego”) and the real party in 8
interest is Rambus, Inc. (“Rambus”). Paper 4. 9
Junior party Perego is involved on the basis of Patent 6,502,161, 10
based on Application 09/479,375, filed January 5, 2000. 11
The senior party is named inventors Robert Allen Drehmel, Kent 12
Harold Haselhorst, Russell Dean Hoover, and James Anthony Marcella 13
(collectively “Drehmel”) and the real party in interest is IBM Corporation 14
(“IBM”). Paper 9. 15
Senior party Drehmel is involved on the basis of Application 16
11/203,652, filed August 15, 2005. 17
Rambus presented claims and sought an interference with IBM. 18
This interference was declared on August 15, 2006. Paper 1. 19
At the time of declaration of interference, Drehmel was accorded 20
benefit of Application 10/747,820, filed December 30, 2003, and 21
Application 09/439,068, filed November 12, 1999. Application 09/439,068 22
is now issued as Patent 6,526,469. 23
Interference No. 105,467
Perego v. Drehmel

3
The sole count is Count 1, which reads (Paper 1, p. 4): 1
Perego 6,502,161 claim 1 2
or 3
Drehmel 11/203,652 claim 11 4
Drehmel’s claim 11 is copied from Perego’s claim 1 and the two 5
claims are identically worded. 6
The claims of the parties are as follows: 7
Perego Patent 6,502,161 1-49 8
Drehmel Application 11/203,652 11-59 9
The claims of the parties which have been designated as 10
corresponding to Count 1 and therefore are involved (35 U.S.C. § 135(a) in 11
the interference) are: 12
Perego Patent 6,502,161 1-49 13
Drehmel Application 11/203,652 11-59 14
The claims of the parties which have been designated as not 15
corresponding to Count 1 and therefore are not involved in the interference 16
are: 17
Perego Patent 6,502,161 None 18
Drehmel Application 11/203,652 None 19
Perego’s claim 1 reads as follows: 20
1. A memory system comprising: 21
22
a memory controller having an interface that includes a 23
plurality of memory subsystem ports; 24
25
a first memory subsystem including: 26
Interference No. 105,467
Perego v. Drehmel

4
1
a buffer device having a first port and a 2
second port, and 3
4
a plurality of memory devices coupled to the 5
buffer device via the second port, wherein data is 6
transferred between at least one memory device of 7
the plurality of memory devices and the memory 8
controller via the buffer device; and 9
10
a plurality of point-to-point links, each point-to-point link 11
of the plurality of point-to-point links having a connection to a 12
respective memory subsystem port of the plurality of memory 13
subsystem ports, the plurality of point-to-point links including a 14
first point-to-point link to connect the first port to a first 15
memory subsystem port of the plurality of memory subsystem 16
ports. 17
18
C. The invention 19
The invention of Count 1 is readily understood by reference to 20
Fig. 3A of Perego’s U.S. Patent 6,502,161 (Ex. 2001). 21
Interference No. 105,467
Perego v. Drehmel

5
1
2
Perego’s Patent Fig. 3A depicts a memory system. 3
With respect to Figure 3A, the disclosed Perego invention is directed 4
to a memory system architecture which includes a memory controller 5
communicating to at least one memory subsystem, e.g., a buffered memory 6
module. (Ex. 2001 3:48-51). An independent point-to-point link is used 7
between the controller and each memory subsystem to eliminate physical 8
inter-dependence between memory subsystems. (Ex. 2001 3:51-54). 9
Memory subsystem 300 includes a controller 310, a plurality of point-10
to-point links 320a-320n, and a plurality of memory subsystems 330a-330n. 11
(Ex. 2001 5:49-52). A more detailed embodiment of memory subsystem 12
330a is illustrated as element 340 also in Figure 3A. Buffer device 350 and 13
a plurality of memory devices 360 are disposed on memory subsystem 340. 14
Interference No. 105,467
Perego v. Drehmel

6
(Ex. 2001 5:54-55). An interface 375 is disposed on controller 310 and it 1
includes a plurality of memory subsystem ports 378a-378n. (Ex. 2001 5:57-2
58). A memory subsystem port sends and receives sends and receives data, 3
addressing and controlling information, over one of the point-to-point links 4
320a-320n. (Ex. 2001 5:60-63). 5
A major contrast with the prior art lies in the difference between the 6
use of individual point-to-point links in Perego’s invention to connect the 7
memory controller and each memory subsystems on the one hand, and the 8
use of a common bus line to do the same on the other. Figure 1 of Perego’s 9
Patent 6,502,161, is reproduced below, illustrating prior art using a common 10
bus line: 11
12
Perego’s Patent Fig. 1 depicts a memory system. 13
In the prior art system shown above, the address lines and control 14
signals of control/address bus 130 are bussed and “shared” between each of 15
modules 120a-120c to provide row/column addressing and read/write, 16
Interference No. 105,467
Perego v. Drehmel

7
precharge, refresh commands, etc., to memory devices on a selected one of 1
modules 120a-120c. (Ex. 2001 1:35-39). 2
Figure 2A of Perego’s Patent 6,502,161, is reproduced below, 3
illustrating a more improved prior art using a common bus 260 with 4
shortened stub lines connecting to each module (Ex. 2001 2:31-40): 5
6
Perego’s Patent Figure 2A depicts a memory system 7
The common bus line or Rambus Channel 260 connects to each 8
memory module through respective short stub lines which tap into the 9
common bus line at a corresponding Memory Translator Hub (MTH) 10
serving as a connection point between the memory module and the bus. 11
(Ex. 2001 2:34-40). 12
Detailed internal connections at each MTH are not illustrated. 13
Although the S-RIMM memory modules appear serially connected rather 14
Interference No. 105,467
Perego v. Drehmel

8
than connected in parallel, in fact they are still connected in parallel to the 1
common bus line 260 through the MTHs. 2
A serial connection contradicts the description of line 260 as a 3
common bus with a termination point beyond the last connected module. 4
In Figure 2A of Perego’s involved patent, the common bus line or 5
Rambus Channel is arranged in a visually snakelike or serpentine daisy 6
chain configuration which winds its way from one MTH hub to the next, 7
switching entry and exit direction at each subsequent MTH. The snakelike 8
daisychain connects to each module through a respective MTH. 9
As is explained in the Perego specification (Ex. 2001 2:45-48), in the 10
bussed approach of Figure 2A, the signal lines also become loaded with a 11
load capacitance associated with each bus connection point, and the load 12
capacitances connected to multiple points along the length of the signal line 13
may degrade signaling performance. (Ex. 2001 2:56-58). 14
As shown in Perego’s Figure 3A, in Perego’s disclosed invention 15
separate and independent point-to-point links 320a-320n are used to connect 16
the memory controller 310 to the buffer device 350 of each memory module 17
330a-330c (element 340 is an expanded view of a memory module): 18
19
Interference No. 105,467
Perego v. Drehmel

9
1
Perego’s Patent Figure 3A depicts a memory system 2
The term “point-to-point link” is expressly defined in Perego’s 3
specification as follows (Ex. 2001 7:39-43): 4
The term “point-to-point link” denotes one or a plurality 5
of signal lines, each signal line having only two transceiver 6
connection points, each transceiver connection point coupled to 7
transmitter circuitry, receiver circuitry or transceiver circuitry. 8
9
Perego’s Figure 3B discloses an alternative invention, one in which 10
the point-to-point links do not connect the common memory controller 310 11
directly to the buffer device 350 in individual memory modules 330a-330c, 12
but to a connector 380a-380n which is in turn connected to a corresponding 13
matching connector 390a-390c on the memory module. And then the buffer 14
device in the memory module is connected through another link to the 15
Interference No. 105,467
Perego v. Drehmel

10
connector 390a-390c (The reference 370a in Figure 3B is believed to be 1
intended as 390a). Perego’s Figure 3B is reproduced below: 2
3
Perego’s Patent Figure 3B depicts a memory system 4
With respect to the alternative invention of Figure 3B, Perego’s 5
specification states (Ex. 2001 6:14-24): 6
Corresponding mating connectors 380a-380n are connected to a 7
connection point of each point-to-point link 320a-320n. Each 8
of mating connectors 380a-380n interface with connectors 9
390a-390c to allow removal/inclusion of memory subsystems 10
330a-330c in memory system 305. In one embodiment, mating 11
connectors 380a-380n are sockets and connectors 390a-390c 12
are edge connectors disposed on an edge of each substrate 13
330a-330c. Mating connectors 380a-380n, are attached to a 14
common substrate shared with point-to-point connections 320a-15
320n and controller 310. 16
17
Interference No. 105,467
Perego v. Drehmel

11
Perego’s specification expressly limits the number of transceiver 1
connection points on a point-to-point link to only two. (Ex. 2001 7:39-43). 2
Perego’s Figure 3B illustrates point-to-point links 320a-320n each of 3
which connects memory controller 310 to a connector 380a-380n. The 4
connector is not a transmitter, receiver, or transceiver, but each point-to-5
point link has two transceiver connection points. 6
One end point of each point-to-point link is coupled to the memory 7
controller 310. The other end point of the same link is coupled to a 8
connector 380a-380n which is coupled to memory controller 310 by the link 9
itself. A transceiver connection point does not require a direct connection to 10
a transmitter, receiver, or transceiver. 11
As shown in Figure 3B, on each point-to-point link 320a-320n, the 12
connection point at each connector 380a-380n is a transceiver connection 13
point, constituting the second transceiver connection point for the point-to-14
point link 320a-320n. An annotated copy of Figure 3B is reproduced below, 15
with added red arrows pointing to the two transceiver connection points of 16
each point-to-point link 320a-320n: 17
Interference No. 105,467
Perego v. Drehmel

12
1
Perego’s Patent Figure 3B depicts a memory system 2
Each connection from memory controller 310 to a buffer device 350 3
in a memory module 330 (illustrated in more detail as element 340) includes 4
more than two transceiver connection points, the two shown above in red for 5
each point-to-point link 320a-320n, one at the immediate and final 6
connection to the buffer device 350 itself, one at the interface connector 390 7
to which the buffer device 350 is connected, and one at the junction between 8
connectors 390 and 380. 9
Together there are five transceiver connection points between the 10
memory controller and each buffer device 350. At the very least, there are 11
three transceiver connection points even if reference numeral 390 does not 12
identify a separate connector. 13
As shown in Figure 3B, the link from memory controller 310 all the 14
way to a buffer device 350 is not a point-to-point link which by definition 15
Interference No. 105,467
Perego v. Drehmel

13
can have no more than two transceiver connection points. Perego’s 1
specification also does not describe that connection as a point-to-point link. 2
D. Priority dates alleged in motions 3
In its priority motion before us, Perego contends that it has established 4
the following dates of conception of the invention of Count 1. 5
6
Event Perego
Conception 14 May 1999
Conception 15 June 1999
Conception 25 June 1999
7
To prevail in its priority motion, Perego must establish one of the 8
three alleged conception of invention dates together with reasonable 9
diligence in reducing the conceived invention to practice from a time just 10
prior to Drehmel’s entry into the field (a date yet to be determined) until 11
January 5, 2000, the time of filing of Perego’s involved Patent 6,502,161. 12
E. Principles of law 13
Conception is the formation "in the mind of the inventor of a definite 14
and permanent idea of the complete and operative invention, as it is 15
therefore to be applied in practice." Coleman v. Dines, 754 F.2d 353, 359 16
(Fed. Cir. 1985). Proof of conception must demonstrate possession of every 17
single feature of the count. Davis v. Reddy, 620 F.2d 885, 889 (CCPA 18
1980). 19
Conception also must be proved by corroborating evidence which 20
shows that the inventor disclosed to others his complete thought expressed in 21
such clear terms as to enable those skilled in the art to make the invention. 22
Interference No. 105,467
Perego v. Drehmel

14
Coleman, 754 F.2d at 359. However, there is no final single formula that 1
must be followed in proving corroboration. Berry v. Webb, 412 F.2d 261, 2
266 (CCPA 1969). Rather, the sufficiency of corroborative evidence is 3
determined by a "rule of reason." Price v. Symsek, 988 F.2d 1187, 1195 4
(Fed. Cir. 1993); Berry, 412 F.2d at 266. 5
A deciding tribunal must make a reasonable analysis of all of the 6
pertinent evidence to determine whether the inventor's testimony is credible. 7
Price, 988 F.2d at 1195. The purpose of requiring corroboration is to 8
prevent fraud by providing independent confirmation of the inventor's 9
testimony. See Berry, 412 F.2d at 266; Reese v. Hurst, 661 F.2d 1222, 1225 10
(CCPA 1981) ("[E]vidence of corroboration must not depend solely on the 11
inventor himself."). 12
13
F. Perego’s alleged conception of 14 May 1999 14
Findings of fact 15
The named inventors of Perego’s involved Patent 6,502,161, are 16
Richard E. Perego, Stefanos Sidiropoulos, and Ely Tsern. 17
Upon joining Rambus on April 1, 1999, Mr. Perego was assigned to 18
the Logical Architecture Group managed by Dr. Ely Tsern. (Ex. 2143 ¶¶ 1-19
3, 6; Ex. 2144 ¶¶ 1, 5; Ex. 2145 ¶ 5). 20
By at least May 14, 1999, Mr. Perego wrote a technical specification 21
titled “3D Parallel Rendering Architecture Proposal” which is Exhibit 2059 22
in this interference. (Ex. 2143 ¶ 11; Ex. 2144 ¶ 10; Ex. 2145 ¶ 9; Ex. 2148 23
¶ 4). Hereinafter, we will refer to that document (Ex. 2059) as “the May 14th 24
Parallel Rendering Proposal.” 25
Interference No. 105,467
Perego v. Drehmel

15
Figure 3-1 of the May 14th Parallel Rendering Proposal is reproduced 1
below, together with the sentence introducing the figure and the associated 2
listing of the applicable nomenclature: 3
4
Figure 3-1 discloses a memory system including a memory controller 5
GMCH. The GMCH is connected by two channels A and B to a first 6
memory module G-RIMM. Configured on the first memory module are two 7
Rendering Hubs (RH) (Ex. 2059 3-13:2-3). Each Rendering Hub RH serves 8
as a buffer to which a separate plurality of memory units are connected. 9
Behind the first memory module are a plurality of additional memory 10
modules of like configuration. The multiple memory modules are described 11
in the written portion of the May 14th Parallel Rendering Proposal as 12
connected to each other via either an inline bus or a snakelike daisy chain 13
Interference No. 105,467
Perego v. Drehmel

16
(Ex. 2059 3-13:7-8). The embodiment illustrated in Figure 3-1 has the 1
“snakelike daisy chain” configuration (Ex. 2059 3-13:7-10). 2
A “snakelike daisy chain” configuration is one depicting a serial 3
connection. According to Computer Dictionary, Second Edition, Microsoft 4
Press (1994), the term “daisy chain” refers to: “[a] set of devices connected 5
in a series.” The definition is sufficiently broad to cover a configuration that 6
merely appears to depict a serial connection but is in fact an inline bus which 7
connects to multiple elements in parallel. 8
As is discussed above, the prior art system shown in Figure 2A of 9
Perego’s involved patent illustrates a plurality of memory modules (S-10
RIMM) which are actually connected in parallel to the Rambus channel 260 11
but in a serpentine winding configuration that illustrates a snakelike daisy 12
chain of modules seemingly connected in series because of short stub lines. 13
Each communication link in a serial connection need not be free of 14
other system components or intermediate connectors. For instance, as is 15
illustrated in Figure 3-1 of the May 14th Parallel Rendering Proposal, the 16
communication link from the memory controller GMCH to one buffer 17
device RH via Channel A is broken up into two segments joined by a 18
connector at an interface to the memory module. Likewise, the 19
communication link from the memory controller GMCH to the other buffer 20
device RH via Channel B is also broken up into two segments joined by a 21
connector at another interface to the memory module. 22
Channel A connects to the memory controller GMCH and Channel B 23
separately connects to the memory controller GMCH. (Ex. 2059 Fig. 3-1). 24
Channel A connects to a connector, shown as a rectangular element on the 25
perimeter of memory module G-RIMM. Channel B connects to a separate 26
Interference No. 105,467
Perego v. Drehmel

17
connector, also shown as a rectangular element on the perimeter of memory 1
module G-RIMM. (Ex. 2059 Fig. 3-1). 2
A first buffer device (RH) on the left side of memory module G-3
RIMM is connected through a first port of its own to the port or connector 4
on the G-RIMM to which Channel A is connected, and a second buffer 5
device (RH) on the right side memory module G-RIMM is connected 6
through a first port of its own to the port or connector on the G-RIMM to 7
which Channel B is connected. (Ex. 2059 Fig. 3-1). The communication 8
link between memory controller GMCH and the first buffer device and the 9
communication link between memory controller GMCH and the second 10
buffer device do not overlap. Each buffer device RH on memory module G-11
RIMM, through a second port of its own, connects to a plurality of memory 12
units. (Ex. 2059 Fig. 3-1). 13
The communication link from memory controller GMCH to the first 14
port of the buffer device RH on the left side of memory module G-RIMM is 15
not a point-to-point link. The two points of connection to the intermediate 16
connector are two additional transceiver connection points on the 17
communication link other than the two end points. 18
The communication link from memory controller GMCH to the first 19
port of the buffer device RH on the right side of memory module G-RIMM 20
is not a point-to-point link. The two points of connection to the intermediate 21
connector are two additional transceiver connection points on the 22
communication link other than the two end points. 23
As shown in Figure 3-1 of the May 14th Parallel Rendering Proposal, 24
each communication link from the memory controller GMCH to a buffer 25
device RH (“Rambus Hub”) includes two segments, a first segment 26
Interference No. 105,467
Perego v. Drehmel

18
extending from the memory controller GMCH to a connector on a memory 1
module including the buffer device, and a second segment from that 2
connector to the buffer device. An annotated copy of Figure 3-1 is 3
reproduced below, with added red arrows pointing to where the first and 4
second segments of the communication link connect to an intermediate 5
connector: 6
7
8
As illustrated in the May 14th Parallel Rendering Proposal, each 9
communication link between the memory controller GMCH and a buffer 10
device RH includes four transceiver connection points, with each transceiver 11
connection point coupled to transmitter circuitry, receiver circuitry, or 12
transceiver circuitry. 13
The intermediate connector is not a transmitter, receiver, or a 14
transceiver circuitry. But each point of connection identified by a red arrow 15
in the annotated Figure 3-1 of the May 14th Parallel Rendering Proposal 16
Interference No. 105,467
Perego v. Drehmel

19
above is coupled by a communication link segment to either the memory 1
controller GMCH or a buffer device RH which is transceiver circuitry. 2
On Page 3-19 of the May 14th Parallel Rendering Proposal, in the 3
section listing the advantages of the design, lines 27-33 state the following: 4
For large capacity designs (8 to 16 DRAMs per G-RIMM), it is 5
possible to reduce the pin count and associated cost of the 6
DRAMs by using a narrower device width (x4, for example) 7
and accessing all devices in parallel, while preserving 8
bandwidth. This potentially enables point-to-point, 9
unidirectional, differential signalling, which could increase 10
bandwidth further. Write buffering in RH could allow a 11
narrower, unidirectional write data bus (x2 for example) if an 12
appropriate stall mechanism is devised. 13
14
The “point-to-point” signalling referred to in the above-quoted 15
discussion is directed to communication in each memory module G-RIMM 16
to DRAM memory devices shown in Figure 3-1 as small rectangles in each 17
G-RIMM, and not communication from a memory controller GMCH to a 18
plurality of G-RIMMs through a buffer in each G-RIMM. 19
Analysis 20
For its priority motion, party Perego bears the burden of proof to 21
establish that it is entitled to the relief requested. 37 C.F.R. § 41.121(b). 22
Conception is the formation in the mind of the inventor of a definite 23
and permanent idea of the complete and operative invention, as it is 24
therefore to be applied in practice, Coleman v. Dines, 754 F.2d at 359, and 25
proof of conception must demonstrate possession of every single feature of 26
the count. Id.; Davis v. Reddy, 620 F.2d at 889. Every limitation of the 27
count must have been known to the inventor at the time of the alleged 28
conception. Coleman v. Dines, 754 F.2d at 359. 29
Interference No. 105,467
Perego v. Drehmel

20
A particular feature of the count is: 1
a plurality of point-to-point links, each point-to-point link of the 2
plurality of point-to-point links having a connection to a 3
respective memory subsystem port of the plurality of memory 4
subsystem ports, the plurality of point-to-point links including a 5
first point-to-point link to connect the first port to a first 6
memory subsystem port of the plurality of memory subsystem 7
ports. 8
9
In his declaration testimony (Ex. 2143 ¶ 19), inventor Richard E. 10
Perego refers to the May 14th Parallel Rendering Proposal, in particular 11
Figure 3-1, which has been reproduced above. Also citing page 19 of the 12
May 14th Parallel Rendering Proposal, and without meaningful explanation, 13
the testimony in the same paragraph further states that as disclosed, “the 14
channels” (Channels A and B in Figure 3-1) could be point-to-point and 15
allow for unidirectional, and differential signalling, which could increase 16
bandwidth. For reasons discussed below, we do not credit that testimony of 17
Richard Perego. Nothing in the law requires the fact finder to credit the 18
unsupported assertions of a witness. See Rohm and Haas Co. v. Brotech 19
Corp., 127 F.3d 1089, 1092 (Fed. Cir. 1997). 20
The pertinent description on page 19 of the May 14th Parallel 21
Rendering Proposal is that appearing on lines 27-33. The entire paragraph 22
has been reproduced above. As is determined in our finding above, the 23
description is directed to signalling in each memory module G-RIMM to a 24
plurality of DRAM memory devices shown in Figure 3-1 as small rectangles 25
in each G-RIMM, and not communication from a memory controller GMCH 26
to a plurality of G-RIMMs through a buffer in each G-RIMM. Channels A 27
and B connecting memory controller GMCH to a memory module G-RIMM 28
Interference No. 105,467
Perego v. Drehmel

21
are plainly not the subject of that discussion, and Perego’s declaration does 1
not explain why Channels A and B are what is discussed. Perego who has 2
the burden of proof has not established that the passage actually refers to 3
communication between controller GMCH and the G-RIMM modules. 4
Paragraph 17 of the supporting declaration of Dr. Steven Woo (Ex. 5
2145), the Technical Director of Rambus, Inc., embodies the same 6
deficiencies as noted above with regard to the declaration of Richard Perego 7
in connection with the point-to-point link requirement for the link between 8
the memory controller GMCH and the buffer in memory module G-RIMM. 9
He does not explain why the passage in lines 27-33 on page 3-19 of the May 10
14th Parallel Rendering Proposal, which on its face concerns communication 11
within the G-RIMM module to and from the plurality of DRAMs, describes 12
the external link from controller GMCH to buffer RH of each G-RIMM. 13
Accordingly, we also do not credit his testimony that the May 14th Parallel 14
Rendering Proposal describes the point-to-point link feature of the count. 15
Co-inventor Dr. Ely Tsern testified that he recalls seeing Richard 16
Perego’s Parallel Rendering Proposal (Exhibit 2059) or a document 17
containing substantially the same information on or about May 13, 1999. 18
(Ex. 2144 ¶ 10). Citing to page 3-19 of the Parallel Rendering Proposal, Dr. 19
Tsern, like Dr. Steven Woo and Richard Perego himself, states that Richard 20
Perego “discloses that Channels A and B may be point-to-point links.” (Ex. 21
2144 ¶ 10). As is already discussed above in connection with Dr. Woo and 22
Richard Perego’s testimony, Dr. Tsern’s testimony concerning Channels A 23
and B in the Parallel Rendering Proposal being described in that proposal as 24
possibly point-to-point links lacks reasonable support and thus is also not 25
credited with persuasive weight. Nothing on page 3-19 of the proposal 26
Interference No. 105,467
Perego v. Drehmel

22
describes that either Channel A or Channel B in Figure 3-1 of the Parallel 1
Rendering Proposal may be a point-to-point link. Dr. Tsern also does not 2
point to any particular part of that page of the proposal. And Dr. Ely Tsern 3
is himself a co-inventor and cannot provide the necessary independent 4
corroboration for an inventive fact. See Brown v. Barbacid, 276 F.3d 1327, 5
1335 (Fed. Cir. 2002). 6
That the signaling between the buffer RH in each G-RIMM module 7
and the plurality of DRAMs in the G-RIMM module may be through point-8
to-point links does not mean the connection from memory controller GMCH 9
to buffer RH in each G-RIMM module has to be through a point-to-point 10
link. Even assuming that the former would have rendered obvious the latter, 11
it does not establish conception by junior party’s inventors of the feature of 12
using a plurality of point-to-point links which connect to a respective port on 13
the memory controller, including one which connects to the buffer. The test 14
for conception is not obviousness. Perego must demonstrate possession of 15
every single feature of the count. Davis v. Reddy, 620 F.2d at 889. 16
In any event, and adding to the deficiency of Perego’s motion, it is 17
noted that the term “point-to-point link” has a special definition in the 18
specification of Perego’s involved patent. (Ex. 2001 7:39-43). Perego has 19
not demonstrated that that special definition is the same as the ordinary 20
meaning of that term in the art of the invention of the count. Thus, on this 21
record it is not even clear whether “point-to-point link” means the same in 22
Perego’s specification and in the May 14th Parallel Rendering Proposal. 23
We have also determined in the findings above that as illustrated in 24
Figure 3-1 of the May 14th Parallel Rendering Proposal, the Channel A link 25
in the portion between memory controller GMCH and buffer RH has four 26
Interference No. 105,467
Perego v. Drehmel

23
transceiver connection points, and the Channel B link in the portion between 1
memory controller GMCH and buffer RH also has four transceiver 2
connection points. As is defined in the specification of Perego’s patent, 3
however, a point-to-point link can have no more than two transceiver 4
connection points. (Ex. 2001 7:39-43). Thus, the portion of Channels A and 5
B shown in Figure 3-1 of the May 14th Parallel Rendering Proposal between 6
memory controller GMCH and buffers RH are not point-to-point links. 7
In addition, each of Channels A and B does not simply terminate at 8
the buffer RH of the first memory module G-RIMM. It winds its way 9
through each successive memory module G-RIMM in a snakelike daisy 10
chain configuration. The segment between memory controller GMCH and 11
the buffer RH of the first G-RIMM is just one portion of the entire channel, 12
and extends continuously to the next segment connecting to the G-RIMM 13
next in line in the daisy chain. Consequently, there are even more 14
transceiver connection points on the same channel and coupled to the 15
segment between memory controller GMCH and the first G-RIMM module, 16
further disqualifying that segment as a point-to-point link. 17
Perego’s motion further refers to an electronic mail message dated 18
May 13, 1999, from Mr. Sheffler (Ex. 2058), which states “Using 19
buffers/repeaters on a module (as described by Rich) is one possibility.” 20
That expression does not indicate the use of a point-to-point link from any 21
component to any other component. 22
In Paragraph 19 of inventor Richard E. Perego’s declaration, he notes 23
that in the May 14th Parallel Rendering Proposal he described that the 24
memory controller and the memory modules may be connected by way of a 25
“snakelike daisy chain.” The daisy chain configuration is described on page 26
Interference No. 105,467
Perego v. Drehmel

24
3-13 as being “illustrated below,” i.e., Figure 3-1. Richard E. Perego further 1
states in the same declaration paragraph that in a “snakelike daisy chain,” the 2
memory controller is connected to the rendering engine of the first memory 3
module by a point-to-point link, and that subsequent memory modules are 4
connected via a separate and isolated set of point-to-point links. Mr. Perego 5
cites page 18 of the May 14th Parallel Rendering proposal, but nothing on the 6
cited page supports the assertion. 7
Moreover, as we have already explained in detail above in connection 8
with the daisy chain configuration illustrated in Figure 3-1, the link from 9
memory controller GMCH to the rendering engine, a buffer, of the first 10
memory module G-RIMM, is not a point-to-point link based on the 11
definition of “point-to-point link” given in Perego’s specification. There are 12
at least four transceiver connection points on that first link, and subsequent 13
links are all segments of the same Channel A or Channel B which connects 14
all of the modules G-RIMM. Each of the segments is connected to all of the 15
transceiver connection points located on the same channel. 16
Note also that if indeed there are separate and isolated segments 17
connecting each successive module, there would have to be circuitry in each 18
G-RIMM module designed for handling information that is received but 19
intended for another module. No such circuitry is described as present 20
within any G-RIMM module. The evidence does not support the assertion 21
that the memory controller GMCH is connected to a first G-RIMM module 22
by a point-to-point link, or that subsequent successive pairs of G-RIMM 23
modules are each connected by a separate and isolated point-to-point link. 24
Mr. Perego’s assertion is contrary to the disclosure of the May 14th 25
Parallel Rendering Proposal itself. We credit the disclosure of the May 14th 26
Interference No. 105,467
Perego v. Drehmel

25
Parallel Rendering Proposal more than the unsupported characterization of 1
Richard E. Perego. We note also the prior art illustrated in Figure 2A of 2
Perego’s involved patent. It is in a “snakelike daisy chain” configuration 3
and yet described in Perego’s involved patent as employing a common 4
channel or bus 260. (Ex. 2001 2:34-48). A common bus that connects all of 5
the G-RIMM modules is neither a point-to-point link nor a plurality of point-6
to-point links. We are unpersuaded by Richard E. Perego’s testimony that 7
the May 14th Parallel Rendering Proposal describes a point-to-point link 8
connecting memory controller GMCH to a buffer of a G-RIMM module. 9
G. Perego’s alleged conception of 15 June 1999 10
In the alternative, Perego alleges conception of the subject matter of 11
the count by June 15, 1999. Perego relies on all of the evidence discussed 12
above in connection with the alleged conception by May 14, 1999, and 13
additional evidence. In particular, Perego relies on another document said to 14
have been generated by Richard E. Perego and shared with his colleagues by 15
June 15, 1999, which is said to be a slightly modified version of the May 16
14th Parallel Rendering Proposal. Hereinafter, the document is referred to as 17
“Parallel Rendering Proposal 2” and it is Exhibit 2063 in the record. 18
Drs. Woo and Tsern testified that they received Parallel Rendering 19
Proposal 2 from Richard E. Perego on June 15, 1999. (Ex. 2145 ¶ 18; Ex. 20
2144 ¶ 11). Perego represents (Motion 12:19-22) that Parallel Rendering 21
proposal 2 and the May 14th Parallel Rendering proposal “are substantially 22
the same, and do not differ in any relevant respect.” Accordingly, we 23
assume that the two documents have the same content and the findings we 24
have made above with respect to the May 14th Parallel Rendering proposal 25
are equally applicable to Parallel Rendering Proposal 2. 26
Interference No. 105,467
Perego v. Drehmel

26
For the same reasons as explained above on why Perego has failed to 1
demonstrate conception of the subject matter of the count by May 14, 1999, 2
Perego has also failed to demonstrate conception of the subject matter of the 3
count by June 15, 1999. 4
H. Perego’s alleged conception of 25 June 1999 5
In the alternative, Perego alleges conception of the subject matter of 6
the count by June 25, 1999. Perego relies on all of the evidence discussed 7
above in connection with the alleged conception by June 15, 1999, and 8
additional evidence. In particular, Perego relies on another document said to 9
have been generated by Richard E. Perego by June 25, 1999, which is said to 10
be a revised version of the May 14th Parallel Rendering Proposal and Parallel 11
Rendering Proposal 2. Hereinafter, the document is referred to as “Parallel 12
Rendering Proposal 3” and it is Exhibit 2065 in the record. 13
Perego represents (Motion 14:3-4) that Parallel Rendering Proposal 3 14
is substantially the same as Parallel Rendering Proposal 2 and the May 14th 15
Parallel Rendering Proposal. Also, Perego asserts (Motion 14:5-6) that 16
Parallel Rendering Proposal 3 satisfies the subject matter of the count for 17
similar reasons as Parallel Rendering Proposal 2 and the May 14th Parallel 18
Rendering Proposal. Accordingly, we assume that the documents have the 19
same substantive content and the findings and conclusions we have made 20
above with respect to the May 14th Parallel Rendering proposal are equally 21
applicable to Parallel Rendering Proposal 3. 22
In ¶ 22 of Richard E. Perego’s declaration (Ex. 2143), it is noted that 23
page 9 of Parallel Rendering Proposal 3 states: “High-bandwidth memory 24
access for Rendering Engine(s) - generally allows point-to-point connections 25
which allow higher interface frequency.” The same disclosure is noted by 26
Interference No. 105,467
Perego v. Drehmel

27
Dr. Steven Woo in ¶ 19 of his declaration. (Ex. 2145). As is the case with 1
cited portions on page 3-19 of the May 14th Parallel Rendering Proposal 2
already discussed, however, the cited text refers to communication between 3
the Rendering Engines and the plurality of memory units (RAMs) all 4
contained within each G-RIMM module, and not to connections between the 5
external memory controller GMCH and each Rendering Engine. Perego has 6
not explained why the converse is true, i.e., why the reference to point-to-7
point connections refers to links between the memory controller and each G-8
RIMM module rather than the links between the Rendering Engine and each 9
random access memory RAM. 10
Dr. Tsern testified that on June 17, 1999, he received an email (Ex. 11
2064) from Richard Perego, which email noted an idea involving buffered 12
solutions with point-to-point differential links. (Ex. 2144, ¶ 11). But the 13
email does not identify or explain the point-to-point links as existing 14
between the memory controller and each buffer, and not between each buffer 15
and the memory RAM units connected to each buffer. It is not enough to 16
show conception that point-to-point links are used somewhere. 17
Also, Dr. Tsern further testified that he “would have understood” the 18
idea in Richard Perego’s email as referring to Richard Perego’s “buffered 19
module concept that is the subject matter of the count” (Ex. 2144, ¶ 11). He 20
does not state that he actually “understood” the matter as such, but “would 21
have understood” as in a speculation. And that does not matter, because 22
Perego has not established that there ever was an inventive concept by June 23
17, 1999, or even June 25, 1999, that was the same as the subject matter of 24
the count. Thus, the testimony in that regard is speculative and unsupported. 25
Interference No. 105,467
Perego v. Drehmel

28
Additionally, Dr. Tsern is a co-inventor and cannot provide the independent 1
corroboration that is required. See Brown v. Barbacid, 276 F.3d at 1335. 2
For the reasons discussed above, Perego has also failed to demonstrate 3
conception of the subject matter of the count by June 25, 1999. 4
I. Conclusion 5
Junior party Perego has not established priority of invention over 6
senior party Drehmel. It is not necessary to consider senior party’s priority 7
motion. 8
Because Perego has failed to meet its burden in establishing 9
conception of the subject matter of the count by any one of its three alleged 10
dates of conception, May 14, 1999, June 15, 1999, and June 25, 1999, 11
whether Perego has established reasonable diligence from just prior to 12
Drehmel’s conception to Perego’s filing date is inconsequential. 13
Because Perego’s motion has not established a prima facie case of 14
priority of invention over Drehmel, we need not consider Drehmel’s 15
opposition to Perego’s priority motion, or Perego’s reply. 16
Drehmel’s Miscellaneous Motion 2 to exclude a multitude of Perego 17
exhibits need not be reached, because even without excluding any Perego 18
exhibit Perego’s Motion 9 has not established conception of the subject 19
matter of the count on May 14, 1999, June 15, 1999, or June 25, 1999. 20
J. Order 21
It is 22
ORDERED that Perego’s Motion 9 is denied; 23
FURTHER ORDERED that Drehmel’s Motion 1 is dismissed; and 24
FURTHER ORDERED that Drehmel’s Miscellaneous Motion 2 to 25
exclude Perego’s evidence is dismissed as moot. 26
Interference No. 105,467
Perego v. Drehmel

29
By Electronic Transmission: 1
Counsel for Perego: 2
Barbara Clarke McCurdy, Esq. 3
Naveen Modi, Esq. 4
FINNEGAN, HENDERSON, FARABOW, 5
GARRETT & DUNNER LLP 6
901 New York Avenue, N.W. 7
Washington, D.C. 20001-4413 8
Tel: 202-408-4000 9
Email: Barbara.mccurdy@finnegan.com 10
Email: naveen.modi@finnegan.com 11
12
13
Counsel for Drehmel: 14
15
Anthony M. Zupcic, Esq. 16
Douglas Sharrott, Esq. 17
FITZPATRICK, CELLA. HARPER & SCINTO 18
1290 Avenue of the Americas 19
New York, N.Y. 10104-3800 20
Tel: 212-218-2100 21
Email: azupcic@fchs.com 22
Email: dsharrott@fchs.com 23