Park, Junhyun et al.

Patent Trials and Appeals Board

Feb 21, 2020

15006000 - (D) (P.T.A.B. Feb. 21, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/006,000 01/25/2016 Junhyun Park 080008/411601-00341 8973
23363 7590 02/21/2020
Lewis Roca Rothgerber Christie LLP
PO BOX 29001
Glendale, CA 91209-9001
EXAMINER
LAM, TUAN THIEU
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
02/21/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
pair_cph@firsttofile.com
pto@lrrc.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte JUNHYUN PARK, JONGHEE KIM, SUNGHWAN KIM,
JAEKEUN LIM, and CHONGCHUL CHAI

Appeal 2019-001095
Application 15/006,000
Technology Center 2800
____________

Before MICHAEL P. COLAIANNI, CHRISTOPHER C. KENNEDY, and
MICHAEL G. McMANUS, Administrative Patent Judges.

COLAIANNI, Administrative Patent Judge.

DECISION ON APPEAL

Pursuant to 35 U.S.C. § 134(a), Appellant0F1 appeals from the
Examiner’s decision to reject claims 1 to 18. We have jurisdiction under
35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as Samsung
Display Co., LTD. (Appeal Br. 1).
Appeal 2019-001095
Application 15/006,000

2
Appellant’s invention is directed to a gate driving circuit comprising a
plurality of driving stages that is integrated into a display panel and provides
a display device with better reliability (Spec. ¶ 2; Claim 1).
Claim 1 is representative of the subject matter on appeal:
A gate driving circuit comprising a plurality of driving
stages, wherein an ith driving stage of the plurality of driving
stages comprises:
an output unit configured to output an ith output signal,
the output signal including a high voltage and a low voltage, the
high voltage is generated based on a clock signal in response to
a voltage of a Q-node;
a stabilization unit configured to provide the low voltage
to the Q-node in response to a switching signal applied to an A-
node after the ith output signal is outputted; and
an inverter unit configured to output the switching signal
to the A-node for controlling the stabilization unit, the inverter
unit comprising:
a first inverter transistor configured to provide the
switching signal generated based on the clock signal to
the A-node, in response to a voltage of a B-node;
a second inverter transistor configured to control
the voltage of the B-node based on the clock signal, in
response to the clock signal; and
a third inverter transistor configured to output the
low voltage in response to the ith output signal; and
a fourth inverter transistor configured to be turned
on in a section where the ith output signal is outputted to
deliver an output of the third inverter transistor to the B-
node,
wherein i is a natural number equal to or greater than 2.
Appellant appeals the following rejections:
1. Claims 1 to 11 are rejected under 35 U.S.C. § 103 as unpatentable
over Yoon (US 8,587,347 B2, issued November 19, 2013) in
view of Oshima (US 4,623,908, issued November 18, 1986).
Appeal 2019-001095
Application 15/006,000

3
2. Claims 12 to 18 are rejected under 35 U.S.C. § 103 as
unpatentable over Yoon in view of Oshima and Tobita (US
2008/0101529 A1, published May 1, 2008).
3. Claims 1 to 11 are rejected under 35 U.S.C. § 103 as unpatentable
over Lee (US 2012/0293467 A1, published November 22, 2012)
in view of Oshima.
4. Claims 12 to 18 are rejected under 35 U.S.C. § 103 as
unpatentable over Lee in view of Oshima and Tobita.
Appellant argues the subject matter of claim 1 only (Appeal Br. 3 to
8)1F2.

FINDINGS OF FACT & ANALYSIS
The Examiner’s findings and conclusions regarding the rejection of
claim 1 over Yoon or Lee in view of Oshima are located on pages 2 to 3 and
7 of the Final Action.
Appellant argues the Examiner’s combination of Oshima’s teachings
with Yoon or Lee lacks adequate rationale (Appeal Br. 4). Appellant
contends that the Examiner identifies leakage current through Yoon’s and
Lee’s transistor T13 could be reduced but does not explain why a person of
ordinary skill in the art would have been motivated to reduce the leakage
current through the transistors T13 (Appeal Br. 4). Appellant contends that
the Examiner engaged in impermissible hindsight in finding that a person of
ordinary skill in the art would have placed a fourth transistor in series with

2 The page numbering in the Appeal Brief is not correct. Our reference to
the page numbers presumes the first page of the Appeal Brief as page 1 and
the remaining pages are numbered in order sequence thereafter.
Appeal 2019-001095
Application 15/006,000

4
Yoon’s or Lee’s transistor T13 (Appeal Br. 7). Appellant argues that the
Examiner has not shown that Yoon’s or Lee’s transistor T13 suffers from
leakage current that would benefit from having an additional transistor in
series with T13 (Appeal Br. 7).
The preponderance of the evidence favors Appellant’s argument of
non-obviousness. The Examiner finds that Yoon or Lee teach all the
limitations recited in claim 1 except for “a fourth inverter transistor
configured to be turned on in a section where the ith output signal is
outputted to deliver an output of the third inverter transistor to the B node.”
(Final Act. 2–3, 7). The Examiner finds that Oshima teaches that a thin film
transistor’s performance suffers from leakage current in an OFF state (Final
Act. 2–3, 7). The Examiner concludes that it would have been obvious to
include an additional transistor in cascading fashion manner with Lee’s or
Yoon’s third inverter transistor T13 for the purpose of reducing leakage
current as taught by Oshima (Final Act. 3, 7; Ans. 8). The Examiner fails to
explain why, absent hindsight, one of ordinary skill in the art would have
modified Yoon’s and Lee’s circuit to place another transistor in series with
the transistor T13. The Examiner’s basis for the modification is that Oshima
teaches that thin film transistor’s performance can suffer from leakage
current in an OFF state (Ans. 12). The Examiner has not shown that leakage
current was an issue with transistor T13 in Lee or Yoon such that using
Oshima’s serially connected transistors would have prevented the current
leakage. The Examiner provides no analysis other than to make a
conclusory statement that the modification would have been made to reduce
current leakage (Final Act. 3, 7).
Appeal 2019-001095
Application 15/006,000

5
The Examiner appears to base the combination on reducing power
consumption by reducing leakage current (Ans. 12). Yoon teaches,
however, that adding thin film transistors (i.e., switching elements) may
consume a large amount of power and be expensive to manufacture (col. 1,
ll. 34–43). In other words, Yoon appears to contradict the Examiner’s
finding that power consumption would be reduced by adding an additional
thin film transistor.
On this record, we conclude the Examiner has not shown that the
claimed subject matter would have been obvious. We are constrained to
reverse the Examiner’s § 103 rejections of claims 1 to 11 over Yoon or Lee
in view of Oshima. We reverse the Examiner’s § 103 rejections of claims 12
to 18 over Yoon or Lee in view of Oshima and Tobita.

CONCLUSION
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–11 103 Yoon, Oshima 1–11

12–18 103 Yoon, Oshima, Tobita 12–18
1–11 103 Lee, Oshima 1–11
12–18 103 Lee, Oshima, Tobita 12–18
Overall
Outcome
1–18

REVERSED