Parag Upadhyaya et al.Download PDFPatent Trials and Appeals BoardNov 4, 201914700695 - (D) (P.T.A.B. Nov. 4, 2019) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/700,695 04/30/2015 Parag Upadhyaya X-4665 US 1071 24309 7590 11/04/2019 XILINX, INC ATTN: LEGAL DEPARTMENT 2100 LOGIC DR SAN JOSE, CA 95124 EXAMINER TADESE, BERHANU ART UNIT PAPER NUMBER 2632 NOTIFICATION DATE DELIVERY MODE 11/04/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): xilinxipl@xilinx.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte PARAG UPADHYAYA, ADEBABAY M. BEKELE, DIDEM Z. TURKER MELEK, and ZHAOYIN D. WU ____________ Appeal 2019-000085 Application 14/700,695 Technology Center 2600 ____________ Before ELENI MANTIS MERCADER, NORMAN H. BEAMER, and GARTH D. BAER, Administrative Patent Judges. MANTIS MERCADER, Administrative Patent Judge. DECISION ON APPEAL Appeal 2019-000085 Application 14/700,695 2 STATEMENT OF THE CASE Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s final rejection of claims 1–5, 7–9, 12–15, 17, and 20. Dependent claims 6, 10, 11, 16, 18, and 19 are objected to and indicated as containing allowable subject matter (Final Act. 11). We have jurisdiction under 35 U.S.C. § 6(b). We affirm. THE INVENTION Appellant’s claimed invention is directed to “providing reconfigurable fractional-N frequency generation for a phase-locked loop (PLL)” in which the “PLL circuit further includes a sigma-delta modulator (SDM)” and “the SDM [is] responsive to an order select signal operable to select an order of the SDM” (Spec. ¶ 3). Independent claim 1, reproduced below, is representative of the subject matter on appeal: 1. A phase-locked loop (PLL) circuit, comprising: an error detector operable to generate an error signal in response to comparison of a reference signal having a reference frequency and a feedback signal having a feedback frequency; an oscillator, coupled to the error detector, operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times the reference frequency; 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies Xilinx, Inc. as the real party in interest (Appeal Br. 3). Appeal 2019-000085 Application 14/700,695 3 a frequency divider, coupled to the oscillator, operable to divide the output frequency of the output signal to generate the feedback signal based on a divider control signal; a sigma-delta modulator (SDM), coupled to the frequency divider, operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM including a plurality of stages that are selectively enabled responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM through the order select signal. Appeal Br. 12 (Claims Appendix). REFERENCES The prior art relied upon by the Examiner in rejecting the claims on appeal is the following: Name Reference Date Koerner US 2013/0069696 A1 Mar. 21, 2013 Upadhyaya US 2014/0091843 A1 Apr. 3, 2014 REJECTION The Examiner made the following rejection: Claims 1–5, 7–9, 12–15, 17, and 20 stand rejected under 35 U.S.C. § 103 as being unpatentable over Upadhyaya and Koerner. Final Act. 4. ISSUES The issues are whether the Examiner erred in finding: Appeal 2019-000085 Application 14/700,695 4 1. the combination of Upadhyaya and Koerner teaches or suggests the limitations of: a sigma-delta modulator (SDM), coupled to the frequency divider, operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM including a plurality of stages that are selectively enabled responsive to an order select signal operable to select an order of the SDM and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM through the order select signal, as recited in independent claim 1, and similarly recited in independent claim 12; and 2. the combination of Upadhyaya and Koerner teaches or suggests the limitation of: a differential amplifier having inputs coupled to ends of the differential output of the current-steering circuit, respectively, and an output coupled to a first end of the differential output of the current-steering circuit, as recited in dependent claim 5, and similarly recited in dependent claim 15. ANALYSIS We have reviewed the Examiner’s rejection in light of Appellant’s arguments. We have considered in this Decision only those arguments Appellant actually raised in the Briefs. Any other arguments Appellant could have made but chose not to make are deemed waived. See 37 C.F.R. § 41.37(c)(1)(iv) (2017). Appeal 2019-000085 Application 14/700,695 5 Claim 1 Regarding the claimed “sigma-delta modulator,” Appellant argues that “in the cited portion, Upadhyaya explicitly states that the SDM is a third order SDM” and “[t]here is no discussion that the SDM can have a different order than a 3rd order” (Reply Br. 2). Similarly, Appellant argues that “the cited portion of Koerner teaches that that the SDM is a third order SDM” (Reply Br. 3) and while another embodiment teaches “two 2nd order SDMs are used instead of one 3rd order SDM,” there “is no discussion of any control signal used to change the order of the SDMs from the second order” (Reply Br. 4). We are not persuaded. Regarding the claimed sigma-delta modulator, the Examiner finds, and we agree, that Upadhyaya teaches a sigma-delta modulator (SDM) (Figs. 3 or 6) that is coupled to a Divider (270), operable [to] generate and provide a divider control signal (Y[n]), as shown in [Fig.] 6, based on inputs to the sigma delta modulator is N-bit factional signal, as discussed in [¶ 25] . . . and also illustrated in Fig. 6. See for example, in Fig. 6, the integer value (N) and fractional value “FRACTION” being inputted to the SDM; [s]aid sigma delta modulator (SDM) include a plurality of stages as described at [¶ 25] . . . and shown in Fig. 3); wherein the SDM is operable to select an order of the SDM from a first order (1), a second order (1-1), and a third order (1-1-1) (see [¶ 25] . . . , Fig. 3). For example, Fig. 3 illustrates a 3rd order MASH structure a configuration the [sic] can be modified to provide a MASH structure of a different order (e.g., first order, second order and/or third order) (Ans. 11). The Examiner further finds, and we agree, that Koerner teaches “a phase locked loop (PLL) circuit which comprise a sigma-delta (Σ-Δ) modulator (SDM), the Sigma-Delta Modulator having a 3rd order multi stage noise shaping (MASH) structure” (Ans. 11, citing Koerner ¶ 17), in which Appeal 2019-000085 Application 14/700,695 6 [t]he sigma-delta modulator supplied with selectable integer- valued input signal selectively enable[s] the SDM to select an order of the multi stage noise shaping (MASH) structure as described in [¶¶ 16, 20, 22] . . . , and illustrated in Fig. 3 (Ans. 11–12). Here, Appellant’s argument that “[t]here is no discussion of any control signal used to change the order of the SDMs from the second order” (Reply Br. 4) is conclusory and fails to discuss the functioning of the Koerner’s “input value r” (Koerner ¶ 16; see also Koerner ¶¶ 19–22 discussing Figs. 3–4) particularly with respect to setting the input equal to zero for one of the SDMs (represented as either input value “a” for SDM1 or “b” for SDM2, in which “R = N+a+b” (Koerner ¶ 19)), which indicates the corresponding SDM does not add to the frequency division ratio because its value equals zero. Regarding the claimed “state machine,” Appellant argues there is no teaching or suggestion in Upadhyaya of setting the order of the SDM or changing the order from the 3rd order. The cited clock signals operate the SDM and do not change the order of the SDM. Further, since the FSM 630 is not coupled to the SDM, there is no way for the FSM 630 to set the order of the SDM (Reply Br. 4–5). We are not persuaded. The Examiner finds, and we agree, that Upadhyaya teaches a State Machine (FSM) 630, which generates coarse frequency selection signal and as shown and set the order of the SDM 240 as described in [¶¶ 25, 33] . . . . See also the illustration in Fig. 3 that the N-bit Fclock signals used to set or adjust the order the SDM Appeal 2019-000085 Application 14/700,695 7 (Ans. 12). Appellant’s argument is conclusory and does not explain, how the cited portions of Upadhyaya, when combined with the teachings of Koerner, fail to teach or suggest the claimed limitation. Accordingly, we sustain the Examiner’s rejection of independent claim 1, and independent claim 12 commensurate in scope, as well as independent claim 20 and dependent claims 2–4, 7–9, 13, 14, and 17 not argued separately.2 Claim 5 Appellant contends that “[w]hile the circuit shown in Fig. 5 of Upadhyaya teaches differential inputs, the circuits are current sources, not differential amplifiers” (Reply Br. 5). We are not persuaded. The Examiner finds, and we agree, that Upadhyaya disclose a current-steering circuit (S1 and S2 in Fig. 5) coupled between the respective pair of current sources (as illustrated in Fig. 5), the current steering circuit having a pair of differential inputs (‘U’ and ‘D’ as shown in Fig. 5-6) coupled to the output of the PFD [Phase Frequency Detector] 260 and a differential output (as shown in Fig. 6 and further described at [¶ 30] . . .); and a differential amplifier having magnitude +Ip and -Ip (as shown in Fig. 5) and having inputs coupled to ends of the differential output of the current-steering circuit, respectively and an output coupled to a first end of the differential output of the current-steering circuit (l.sub.P1 and l.sub.P2 respectively ([¶ 30] . . . , Fig. 5); wherein a second end of the differential output the current-steering circuit is coupled to the LPF [Low Pass Filter] (as described at [¶ 30] . . . the charge pump consists of the amps and as shown in Figs. 2 and 6 2 We note that independent claim 20 is not commensurate in scope to independent claim 1 as independent claim 20 contains no limitation referencing a “state machine.” Appeal 2019-000085 Application 14/700,695 8 the differential output of the charge pump is coupled to the LPF) (Ans. 12–13). Appellant’s argument is conclusory and fails to explain how the cited portions of Upadhyaya, when combined with the teachings of Koerner, fail to teach or suggest the claimed limitation. For example, the Appellant fails to address the Examiner’s findings of the circuit arrangement of Figure 6 including a PFD, differential amplifier, LPF, and charge pump, in which the “differential amplifier [has] . . . magnitude +Ip and -Ip” and “the charge pump consists of the amps and as shown in Figs. 2 and 6 the differential output of the charge pump is coupled to the LPF.” Accordingly, we sustain the Examiner’s rejection of dependent claim 5 and dependent claim 15 commensurate in scope. CONCLUSION The Examiner did not err in finding: 1. the combination of Upadhyaya and Koerner teaches or suggests the limitations of: a sigma-delta modulator (SDM), coupled to the frequency divider, operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM including a plurality of stages that are selectively enabled responsive to an order select signal operable to select an order of the SDM and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM through the order select signal, Appeal 2019-000085 Application 14/700,695 9 as recited in independent claim 1, and similarly recited in independent claim 12; and 2. the combination of Upadhyaya and Koerner teaches or suggests the limitation of: a differential amplifier having inputs coupled to ends of the differential output of the current-steering circuit, respectively, and an output coupled to a first end of the differential output of the current-steering circuit, as recited in dependent claim 5, and similarly recited in dependent claim 15. In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1–5, 7–9, 12– 15, 17, 20 103 Upadhyaya, Koerner 1–5, 7–9, 12–15, 17, 20 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED Copy with citationCopy as parenthetical citation