PANASONIC CORPORATION

Patent Trials and Appeals Board

Oct 20, 2020

14209244 - (D) (P.T.A.B. Oct. 20, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/209,244 03/13/2014 Hitoshi TSUGE 096506-0019 9229
53080 7590 10/20/2020
McDermott Will and Emery LLP
The McDermott Building
500 North Capitol Street, N.W.
Washington, DC 20001
EXAMINER
ENGLISH, ALECIA DIANE
ART UNIT PAPER NUMBER
2625
NOTIFICATION DATE DELIVERY MODE
10/20/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
mweipdocket@mwe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HITOSHI TSUGE
Appeal 2019-003574
Application 14/209,244
Technology Center 2600

Before ERIC B. CHEN, IRVIN E. BRANCH, and
DAVID J. CUTITTA II, Administrative Patent Judges.
CUTITTA, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–3 and 5–7, all of the claims under
consideration.2 We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42(a). Appellant identifies JOLED Inc. as the real party in
interest. Appeal Br. 2.
2 Claim 4 is cancelled. Appeal Br. 16.
Appeal 2019-003574
Application 14/209,244

2
CLAIMED SUBJECT MATTER
Appellant’s claimed subject matter relates to “[a]n organic EL
(electroluminescence) display apparatus [that] has a large number of arrayed
self-luminous organic EL devices.” Spec. ¶ 2.3 According to Appellant, the
claimed display apparatus includes an image signal compensation circuit that
performs compensation on an image signal “when the image signal is larger
than [a] threshold”, and “outputs [the compensated] image signal to the
image display unit.” Id. at ¶ 8. This “can reduce power consumption
especially in [a] dark screen and can display a high quality image free from
luminance unevenness.” Id. at ¶ 87.
Independent claim 1 is reproduced below, with certain limitations at
issue emphasized, and is illustrative of the claimed subject matter:
1. A display apparatus comprising:
an image display unit having a plurality of arrayed pixel
circuits; and
an image signal compensation circuit coupled to the
image display unit, wherein:
each of the pixel circuits includes:
a current light emitting device;
a driving transistor supplying a current to the
current light emitting device; and

3 Throughout this Decision we refer to: (1) Appellant’s Specification filed
March 13, 2014 (“Spec.”); (2) the Final Office Action (“Final Act.”) mailed
June 18, 2018; (3) the Appeal Brief filed October 25, 2018 (“Appeal Br.”);
and (4) the Examiner’s Answer (“Ans.”) mailed February 26, 2019; and
(5) the Reply Brief filed April 2, 2019 (“Reply Br.”).
Appeal 2019-003574
Application 14/209,244

3
a compensating capacitor which is disposed
between a gate and a source of the driving transistor, and
compensates a threshold voltage of the driving transistor,
the image signal compensation circuit includes:
a compensation memory storing compensation
data for compensating mobility dispersion among driving
transistors of the plurality of arrayed pixel circuits, the
compensation data being for all of the plurality of arrayed
pixel, the compensation memory being configured by a
frame memory;
a comparison circuit which compares an image
signal with a threshold value of luminance; and
an arithmetic circuit which outputs a compensated
image signal being compensated by using the
compensation data read from the compensation memory,
the comparison circuit outputs an enabling signal to the
compensation memory and the arithmetic circuit when the
image signal has a luminance larger than the threshold value,
the compensation data is output from the compensation
memory to the arithmetic circuit according to the enabling
signal, and
the image signal compensation circuit outputs the
compensated image signal to the image display unit when the
image signal has the luminance larger than the threshold value,
and outputs the image signal to the image display unit when the
image signal has a luminance smaller than the threshold value.
Appeal Br. 15 (Claims Appendix).
Appeal 2019-003574
Application 14/209,244

4
REFERENCES
The Examiner relies on the following prior art references:4
Name Reference Date
Cain US 5,454,076 Sept. 26, 1995
Kimura US 2006/0022914 A1 Feb. 2, 2006
Kang US 2010/0309187 A1 Dec. 9, 2010
Inoue US 2011/0141149 A1 June 16, 2011
Ochi US 2012/0274615 A1 Nov. 1, 2012
REJECTIONS
The Examiner rejects claims 1, 2, and 7 under 35 U.S.C. § 103(a) as
unpatentable over Ochi, Inoue, and Kimura. Final Act. 2–7.
The Examiner rejects claim 3 under 35 U.S.C. § 103(a) as
unpatentable over Ochi, Inoue, Kimura, and Kang. Id. at 7–8.
The Examiner rejects claims 5 and 6 under 35 U.S.C. § 103(a) as
unpatentable over Ochi, Inoue, Kimura, and Cain. Id. at 8–9.

OPINION
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of Appellant’s arguments and evidence.
Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential).
Independent claim 1 recites, in part, “the comparison circuit outputs
an enabling signal to the compensation memory and the arithmetic circuit
when the image signal has a luminance larger than the threshold value, the
compensation data is output from the compensation memory to the
arithmetic circuit according to the enabling signal.” The Examiner relies on

4 All citations to the references use the first-named inventor or author only.
Appeal 2019-003574
Application 14/209,244

5
Inoue’s storage unit 150 to teach or suggest the claimed comparison circuit
and compensation memory and on Inoue’s signal level correction unit 128 to
teach or suggest the claimed arithmetic circuit. Final Act. 3–4 (citing Inoue
¶¶ 104, 134–139, 146–163, 211–212); Ans. 13–14.
Appellant argues that “the Examiner unreasonably asserted that the
same storage unit 150 of Inoue as the claimed comparison circuit and
compensation memory, which are distinct elements.” Appeal Br. 6
(emphasis omitted). According to Appellant, “[a] DRAM is merely a
memory having only a function of storing data, and does not have other
functions (e.g., comparing an image signal with a threshold value of
luminance), unless otherwise so configured.” Id. Therefore, “Inoue does
not disclose that the storage unit 150 has such an additional function of
comparing an image signal with a threshold value of luminance” and the
storage unit 150 does not output an enabling signal. Id. at 6–7.
Appellant’s arguments are persuasive. The disputed limitation
requires both (i) a comparison circuit and (ii) a compensation memory, but
the Examiner points to a single element––Inoue’s storage unit 150 to teach
or suggest both (i) and (ii). Because the Examiner maps the claimed
“comparison circuit” and “compensation memory” to Inoue’s Synchronous
Dynamic Random Access Memory (“SDRAM”) 150, the Examiner’s
mapping improperly renders the claimed “comparison circuit” superfluous.
See Mangosoft, Inc. v. Oracle Corp., 525 F.3d 1327, 1330–31 (Fed. Cir.
2008) (rejecting claim construction that would render a claim term
superfluous). Also, the Examiner does not sufficiently explain how Inoue’s
SDRAM 150 would compare an image signal with a threshold value of
luminance and based on the comparison, output an enabling signal to itself.
Appeal 2019-003574
Application 14/209,244

6
Appellant’s Specification describes that if image signal V is larger than the
low-luminance threshold, comparison circuit 52 sets the enabling signal to
High and outputs the enabling signal to compensation memory 54 so that
compensation memory 54 may then output compensation data Gx to pixel x.
Spec. ¶ 62. The Examiner, however, does not sufficiently explain why
Inoue’s storage unit 150 would need to output an enabling signal if storage
unit 150 were performing both the comparing of image data to a threshold
and the storing of compensation data, as recited in claim 1.
Because we agree with at least one of the dispositive arguments
advanced by Appellant for claim 1, we need not reach the merits of
Appellant’s other arguments. Accordingly, based on the record before us,
we do not sustain the Examiner’s 35 U.S.C. § 103(a) rejection of
independent claim 1. We also reverse the rejection of dependent claims 2
and 7, for similar reasons.
With respect to the remaining obviousness rejections of claim 3, 5,
and 6, the Examiner does not rely on the additionally cited references, Kang
or Cain, to cure the deficiency noted for claim 1. Accordingly, we do not
sustain these obviousness rejections of these claims for the reasons set forth
above for claim 1.
CONCLUSION
We reverse the Examiner’s decision to reject claims 1–3 and 5–7
under 35 U.S.C. § 103(a).
Appeal 2019-003574
Application 14/209,244

7
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1, 2, 7 103(a) Ochi, Inoue, Kimura 1, 2, 7
3 103(a) Ochi, Inoue, Kimura,
Kang
3
5, 6 103(a) Ochi, Inoue, Kimura,
Cain
5, 6
Overall
Outcome
1–3, 5–7

REVERSED