NXP B.V.

Patent Trials and Appeals Board

Feb 23, 2021

2020000330 (P.T.A.B. Feb. 23, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/867,943 01/11/2018 Hamidreza Hashempour 82073699US01 3978
65913 7590 02/23/2021
Intellectual Property and Licensing
NXP B.V.
411 East Plumeria Drive, MS41
SAN JOSE, CA 95134
EXAMINER
KIM, JUNG H
ART UNIT PAPER NUMBER
2842
NOTIFICATION DATE DELIVERY MODE
02/23/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte HAMIDREZA HASHEMPOUR, JOS VERLINDEN, and
IDS CHRISTIAAN KEEKSTRA
Appeal 2020-000330
Application 15/867,943
Technology Center 2800
Before KAREN M. HASTINGS, JEFFREY B. ROBERTSON, and
N. WHITNEY WILSON, Administrative Patent Judges.
WILSON, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s March 15, 2019 decision to finally reject claims 1–4, 6–8, 10,
12–17, 19, and 22. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

1 We use the word Appellant to refer to “applicant” as defined in
37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as NXP
B.V., which is a wholly owned subsidiary of NXP Semiconductors N.V.
(Appeal Br. 3).
Appeal 2020-000330
Application 15/867,943

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CLAIMED SUBJECT MATTER
The claims are directed to a clock delay circuit (Abstract). As shown
in Appellant’s FIG. 1 below, clock delay circuit 101 includes an output to
provide an output clock signal CLOCKOUT which is a delayed version of
an input clock signal CLOCKIN:

FIG. 1 is a circuit diagram of a clock delay circuit according to an
embodiment of Appellant’s disclosure.

Clock delay circuit 101 includes a delay control circuit 105 which
includes an output for providing a third clock signal CLOCKDC having a
duty cycle. Clock delay circuit 101 also includes a latch 103 with a first
input D to receive the clock input signal CLOCKIN, a second input C to
receive the third clock signal CLOCKDC and an output Q to provide the
output clock signal CLOCKOUT. A delay between the input clock signal
CLOCKIN and the output clock signal CLOCKOUT is dependent on the
duty cycle of the third clock signal CLOCKDC. Claim 1, reproduced below
from the Claims Appendix, is illustrative of the claimed subject matter:
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Application 15/867,943

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1. A clock delay circuit comprising:
an output to provide an output clock signal which is a
delayed version of an input clock signal;
a delay control circuit including an output for providing a
third clock signal having a duty cycle;
a latch including a first input to receive the input clock
signal, a second input to receive the third clock signal, and an
output to provide the output clock signal, wherein a delay
between the input clock signal and the output clock signal is
dependent upon the duty cycle of the third clock signal.
REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Lewis US 8,294,502 B2 October 23, 2012
Kawagoe US 8,907,711 B2 December 9, 2014
REJECTIONS
1. Claims 1, 15, 16, 19, and 22 are rejected under
35 U.S.C. § 102(a)(1) as anticipated by Lewis.
2. Claims 2–4, 6–8, 10, 12–14, and 17 are rejected under
35 U.S.C. § 103 as unpatentable over Lewis in view of Kawagoe.
OPINION
Appellant makes arguments specific to five separate claims (claims 1,
2, 6, 17, and 22) (see, Reply Br. 2). However, because we base our decision
on a limitation found in independent claim and common to all of the claims,
we focus our decision on the anticipation rejection of claim 1. The
remaining claims stand or fall with the claim 1.
Claim 1 – Anticipation by Lewis. “A prior art reference anticipates a
patent claim under 35 U.S.C. § 102(b) if it discloses every claim
limitation.” In re Montgomery, 677 F.3d 1375, 1379 (Fed. Cir. 2012) (citing
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Application 15/867,943

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Verizon Servs. Corp. v. Cox Fibernet Va., Inc., 602 F.3d 1325, 1336–37
(Fed. Cir. 2010)). In this instance, Appellant contends that Lewis does not
teach a latch including a second input to receive the third clock signal,
wherein a delay between the input clock signal and the output clock signal is
dependent upon the duty cycle of the third clock signal (Appeal Br. 12). The
Examiner finds that this feature is disclosed by Lewis, where in response to
the high duty cycle PUL’, OUT goes high as shown in FIG. 3 (depicted
below) after a delay from IN going high:

Lewis’s FIG. 3 is a timing diagram illustrating the behavior of
relevant signals during the operation of the delay circuitry in
accordance with an embodiment of Lewis’s disclosure.

Appellant argues that the Examiner’s finding set forth above is not
supported by Lewis’s disclosure, and that the delay between Lewis’s input
clock signal IN and the output clock signal OUT of the delay circuitry is not
dependent on the duty cycle of the PUL’ signal (Appeal Br. 12–13).
Appellant contends that the PUL’ signal is produced by delay circuit 58,
which delays a pulse signal PUL received by the delay circuit and provides
the PUL’ signal by a delay of TΔ:

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Application 15/867,943

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Delay circuit 58 may serve to provide the desired signal delay
introduced by delay circuitry 50. Delay circuit 58 may have an
input and an output. The input of delay circuit 58 may receive
signal PUL. Delay circuit 58 may be used to introduce a desired
timing delay TΔ. For example, signal PUL may have a rising
edge at time t0. A delayed version of signal PUL may be
generated at the output of delay circuit 58. In particular, the
rising edge of delayed pulse signal PUL’ may be delayed by TΔ
following time t0. Delay circuit 58 may be formed from
inverter chains, delay interpolators, or other types of delay
elements.

(Lewis, 4:49–59). Appellant states that Lewis teaches that although the
delay between the input signal and the output signal is adjusted by adjusting
the delay TΔ between the PUL signal and PUL’ signal, the pulse width Tδ of
the pulses of the PUL signal do not change the delay TΔ between the input
signal IN and the output signal OUT (Appeal Br. 14, citing Lewis 6:18–18
(“The change in pulse width Tδ, however, does not affect delay TΔ”)).
Appellant further argues that the duty cycle of the PUL’ signal
corresponds the relationship between the pulse width Tδ of the pulses of the
PUL’ signal with respect to the period of time of the PUL’ signal and,
therefore, that Lewis is explicit in stating that its delay TΔ is not correlated
with the duty cycle of the PUL’s signal (Appeal Br. 15).
In response, the Examiner finds that the occurrence of the rising edge
of PUL’ with respect to the rising edge of the PUL determines the delay
between IN and OUT, and that because “a duty cycle of a signal includes
both a rising edge and a falling edge” this finding supports a conclusion that
the delay between IN and OUT is dependent upon the duty cycle (i.e., the
rising edge) of the PUL’ (Ans. 3).
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Thus, the determinative issue with regards to the rejection of claim 1 is
whether Lewis’s circuit has its delay dependent upon the duty cycle of the
PUL’ signal. The Examiner argues, based on a claim construction argument,
that Appellant has essentially admitted that Lewis’s disclosure covers claim 1:
[S]uch a feature is disclosed in Lewis in that in response to the
high duty cycle of PUL’, OUT goes high (thus dependent on
the duty cycle of PUL’) as shown in Fig. 3 after a delay from
IN going high). Appellant more specifically argues . . . that the
delay between IN and OUT in Figs. 2–3 of Lewis is not
dependent upon the duty cycle of PUL’ because the delay
between IN and OUT in Figs. 2–3 of Lewis does not depend on
changes to the pulse widths of PUL’. However, such an
argument is not commensurate with the scope of claim 1. Claim
1 requires that a delay between the input clock signal and the
output clock signal is dependent upon the duty cycle of the third
clock signal; claim 1 does not require the delay to be dependent
upon a change in the duty cycle of the third clock signal, as
argued by the Appellant. Appellant further argues (Appeal
Brief at p. 16) that the Final Office Action may be confusing
the occurrence of the rising edge of a signal with the duty cycle
of a signal. However, since a duty cycle includes both the
rising edge and the falling edge of a signal, the duty cycle of
PUL’ includes the rising edge of PUL’. Thus, Appellant’s
admission (Appeal Brief at p. 16) that the occurrence of the
rising edge of PUL’ with respect to the rising edge of the rising
edge of PUL’ determines the delay between IN and OUT
supports the conclusion that the delay between IN and OUT is
dependent upon the duty cycle (e.g., the rising edge) of PUL’.

(Ans. 4, internal citations omitted, emphasis added). We disagree the
Examiner on the claim construction issue and, as discussed below, such
disagreement requires reversal of the rejection.
It is well established that “the PTO must give claims their broadest
reasonable construction consistent with the specification. . . . Therefore, we
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look to the specification to see if it provides a definition for claim terms, but
otherwise apply a broad interpretation.” In re ICON Health & Fitness, Inc.,
496 F.3d 1374, 1379 (Fed. Cir. 2007). In this instance, the relevant claim
language is “wherein a delay between the input clock signal and the output
clock signal is dependent upon the duty cycle of the third clock signal”
(Appeal Br. 12 (emphasis added)). The Examiner determines that, under the
broadest reasonable interpretation standard, this language does not mean that
the delay has to be dependent on a change in the duty cycle of the third signal,
i.e., the PUL’ (Ans. 4).
We disagree with the Examiner. The plain language of the claim
states that the delay is dependent on the duty cycle. That language
necessarily means that if the duty cycle changes, then the delay would
change, which is consistent with the description in the Specification (Spec. ¶
18 (“[d]ecreasing the duty cycle of the clocking signal . . . increas[es] the
delay time”)). We are also mindful that:
[t]he correct inquiry in giving a claim term its broadest
reasonable interpretation in light of the specification is not
whether the specification proscribes or precludes some broad
reading of the claim term adopted by the examiner. And it is not
simply an interpretation that is not inconsistent with the
specification. It is an interpretation that corresponds with what
and how the inventor describes his invention in the
specification, i.e. an interpretation that is consistent with the
specification.

In re Smith Int’l, Inc., 871 F.3d 1375, 1382–83 (Fed. Cir. 2017) (internal
quotation omitted); see also In re Baker Hughes, Inc., 215 F.3d 1297, 1303
(Fed. Cir. 2000) (the PTO cannot adopt a construction that is “beyond that
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which was reasonable in light of the totality of the written description” in the
Specification).
Thus, the proper interpretation of the claim language is that a change in
the duty cycle results in a change in the delay.
Moreover, as explained in detail by Appellant (Appeal Br. 15–16, Reply
Br. 3–4), although a rising edge or falling edge may be considered in
determining the duty cycle of a signal, neither a rising nor a falling edge is part
of a duty cycle. Instead, a duty cycle may be defined as “the ratio between the
pulse duration, or pulse width (PW) and the period (T) of a rectangular
waveform.” In addition, as also explained by Appellant, Lewis explicitly states
that one of the advantages of its system is that its delay is not dependent on the
effects of aging on the pulse width (i.e., the duty cycle) of PUL’.
Accordingly, we determine that Appellant has shown reversible error in
the anticipation of claim 1. Because the rejections of the remaining claims
(each of which depends directly or indirectly from claim 1) rely on the same
erroneous findings with respect to claim 1, we also reverse the rejections of
the remaining claims.

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DECISION SUMMARY
In summary:
Claims
Rejected
35
U.S.C. §
Reference(s)/Basis Affirmed Reversed
1, 15, 16, 19,
22
102 Lewis 1, 15, 16, 19,
22
2–4, 6–8, 10,
12–14, 17
103 Lewis, Kawagoe 2–4, 6–8, 10,
12–14, 17
Overall
Outcome
1–4, 6–8, 10,
12–17, 19, 22

REVERSED