Micron Technology, Inc.

Patent Trials and Appeals Board

Apr 7, 2021

2019006658 (P.T.A.B. Apr. 7, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/172,806 02/04/2014 Umberto Siciliani MI22-5469 5109
21567 7590 04/07/2021
Wells St. John P.S.
601 W. Main Avenue
Suite 600
Spokane, WA 99201
EXAMINER
NGUYEN, WILLIAM V
ART UNIT PAPER NUMBER
2183
NOTIFICATION DATE DELIVERY MODE
04/07/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@wellsip.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte UMBERTO SICILIANI, TOMMASO VALI,
WALTER DI-FRANCESCO, VIOLANTE MOSCHIANO,
and ANDREA SMANIOTTO

Appeal 2019-006658
Application 14/172,806
Technology Center 2100

Before JEAN R. HOMERE, JAMES B. ARPIN, and
MICHAEL J. ENGLE, Administrative Patent Judges.

HOMERE, Administrative Patent Judge.

DECISION ON APPEAL
I. STATEMENT OF THE CASE1
Pursuant to 35 U.S.C. § 134(a), Appellant appeals from the
Examiner’s rejection of claims 1–6, 9–13, 15–18, 20, 23–29, 31–33, and 35–
44, all of the claims pending.2 Appeal Br. 4. Claims 7, 8, 14, 19, 21, 22, 30,

1 We refer to the Specification filed Feb. 4, 2014 (“Spec.”); the Final Office
Action, mailed Sept. 20, 2018 (“Final Act.”); the Appeal Brief, filed Feb. 20,
2019 (“Appeal Br.”); the Examiner’s Answer, mailed July 8, 2019 (“Ans.”);
and the Reply Brief, filed Sept. 9, 2019 (“Reply Br.”).
2 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42(a).
Appellant identifies Micron Technology, Inc. as the real party in interest.
Appeal Br. 4.
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and 34 are canceled. Claims App. We have jurisdiction under
35 U.S.C. § 6(b).
We reverse.
II. CLAIMED SUBJECT MATTER
The claimed subject matter relates to a method and system for
controlling storage of data in main memory 12 by programming memory
cells 14(a), 14(b) contained therein. Spec. ¶¶ 3, 10. Figure 1, reproduced and
discussed below, is useful for understanding the claimed subject matter:

Figure 1 above illustrates memory system 10 including main memory 12
containing array cells 14a, 14b; interfacing with buffers 16a, 16b; control
unit 18; substitution circuitry 20; and algorithm 22 stored in program
memory 23. Id. ¶¶ 10, 12.
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In particular, control unit 18 executes algorithm 22 to control memory
operations by sending first and second sets of executable instructions to
memory cells 14a, 14b, which store the instructions and forward them to
program memory 23. Id. ¶¶ 3, 10, 12.
Claims 1, 13, 18, 24, and 33 are independent. Claim 1, reproduced
below with disputed limitations emphasized, is illustrative:
1. A memory system comprising:
a main memory comprising a plurality of memory cells
individually configured to store data;
program memory configured to store a plurality of first
executable instructions which are ordered according to a first
instruction sequence and a plurality of second executable
instructions which are ordered according to a second instruction
sequence;
substitution circuitry configured to replace one of the
first executable instructions with a substitute executable
instruction;
a control unit configured to execute the first executable
instructions to implement at least one operation with respect to
the storage of the data using the memory cells, wherein the
control unit is configured to execute the first executable
instructions according to the first instruction sequence, to
execute the substitute executable instruction after the execution
of at least some of the first executable instructions, and to
execute the second executable instructions according to the
second instruction sequence as a result of the execution of the
substitute executable instruction; and
wherein some of the memory cells store the second
executable
instructions and the program memory receives the
second executable
instructions from the some memory cells.
Appeal Br. 34 (Claims App.) (emphasis added).

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III. REFERENCES
The Examiner relies upon the following references.3
Name Reference Date
Moyer US 2002/0124161 A1 Sept. 5, 2002
Hsieh US 2005/0071605A1 Mar. 31, 2005
Dawson US 2008/0154804A1 Jun. 26, 2008
Morad US 2008/0263115A1 Oct. 23. 2008
Tashiro US 2009/0019262A1 Jan. 15, 2009
Iwai US 2010/0157693A1 Jun. 24, 2010
Vauclair US 2010/0325402 A1 Dec. 23, 2010
IV. REJECTIONS4
The Examiner rejects claims 1–6, 9–13, 15–18, 20, 23–29, 31–33, and
35–44 as follows:
Claims 1–6, 9, 10, 18, 23–28, 31, 33, 35–37, 39, 40, and 42 stand
rejected as obvious under 35 U.S.C. § 103 over the combination of Hsieh
and Moyer. Final Act. 3–12.
Claims 13, 15, 16, and 41 stand rejected as obvious under 35 U.S.C.
§ 103 over the combination of Hsieh and Iwai. Id. at 12–15.
Claim 29 stands rejected as obvious under 35 U.S.C. § 103 over the
combination of Hsieh, Moyer, and Morad. Id. at 15–16.
Claims 11, 20, 32, and 38 stand rejected as obvious under 35 U.S.C.
§ 103 over the combination of Hsieh, Moyer, and Tashiro. Id. at 16–17.

3 All reference citations are to the first named inventor only.
4 The Examiner withdraws the indefiniteness rejection previously entered
against claim 44. Ans. 38.
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Claim 12 stands rejected as obvious under 35 U.S.C. § 103 over the
combination of Hsieh, Moyer, and Dawson. Id. at 17–18.
Claim 17 stands rejected as obvious under 35 U.S.C. § 103 over the
combination of Hsieh, Iwai, Tashiro, and Moyer. Id. at 18–19.
Claim 43 stands rejected as obvious under 35 U.S.C. § 103 over the
combination of Hsieh, Moyer, and Iwai. Id. at 19–20.
Claim 44 stands rejected as obvious under 35 U.S.C. § 103 over the
combination of Hsieh, Iwai, and Vauclair. Id. at 20–21.
V. ANALYSIS
Appellant argues, inter alia, that the Examiner errs in finding that the
combination of Hsieh and Moyer teaches or suggests a program memory
receiving a second set of executable instructions from the memory cells of
main memory, as recited independent claim 1. Appeal Br. 15–16. In
particular, Appellant argues that Moyer’s disclosure of a redirecting circuitry
of data processing systems for redirecting program flow does not cure the
admitted deficiencies of Hsieh to teach the disputed limitations. Id. at 16–17;
Reply Br. 2–4. More particularly, Appellant argues that Hsieh’s disclosure
of a processing unit executing instructions and a branching executing a patch
located on another memory does not teach or suggest the disputed
limitations. Reply Br. 3 (citing Hsieh ¶¶ 39, 40). Similarly, Appellant
disputes that Moyer’s disclosure of a read-only memory (ROM) including
program code which may use patches located in different locations thereof
or on different memories pertain to redirecting a program flow from a
different memory has nothing to do with a program memory receiving
executable instructions from cells of main memory. Id. at 3–4 (citing Moyer
¶ 19).
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In response, the Examiner finds the following:
Hsieh teaches program memory [memory cells] receiving
the second executable instructions from auxiliary memory
[additional memory cells] that is separate from the main
memory ROM (Hsieh, Fig. 3, paragraph 39-40, patch
instructions [second executable instructions] stored in auxiliary
memory) but does not teach the second executable instructions
being stored memory cells in the main memory. However,
Moyer teaches patching instruction located in main memory
(Moyer, paragraph 19, code patches that may be located either
in a different location within ROM 106 or in other memories
such as [random-access memory (RAM)] 104, ROM 116, RAM
118, or any other memory coupled to processor 102.
Alternatively, ROM 106 may include data accessed by code
executing on processor 102). The combination teaches ROM
and RAM [memory cells] stored together in a centralized
location [main memory] instead of previously separate where
the patch instructions [second executable instructions] are
located. The prior art teaches a central location [main memory]
that holds program memory that is first executed [first
executable instructions to implement at least one operation with
respect to the storage of the data using the memory cells] and
patch program [memory cells of the first and second executable
instructions] from which the patch memory consists of
replacement instructions [program memory receives the second
executable instructions]; therefore, the arguments are
unpersuasive.
Ans. 22–23.
Appellant’s arguments are persuasive of reversible Examiner error.
Hsieh discloses a microcomputer system including a processing unit,
upon receiving an instruction from a controller, branching off a first program
stored in a ROM to execute a patch located on an auxiliary memory. Hsieh
¶¶ 40, 41, Fig. 3. Further, Moyer discloses a data processing system
including a microprocessor executing a code to access data in a ROM as
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well as to execute patch data in the ROM or a RAM coupled thereto. Moyer
¶¶ 18–20.
We do not agree with the Examiner that Hsieh’s auxiliary memory
(identified by Examiner as the program memory including memory cells)
receiving executable instructions from the ROM (identified by Examiner as
main memory) taken in combination with Moyer’s ROM (identified by
Examiner as main memory including memory cells) teaches a program
memory receiving instructions from cells in main memory. Ans. 22. As
noted above, the cited portions of Hsieh and Moyer relate to a controller
instructing a processor to process patches in a ROM or an auxiliary memory.
Appeal Br. 16. Therefore, the proposed combination would at best result in
the auxiliary memory/RAM receiving patches from a ROM. However, we
find insufficient evidence on this record to support the Examiner’s finding
that the patches teach the memory cells recited in the disputed limitations.
Because the record before us is further devoid of sufficient evidence that
Hsieh’s auxiliary memory or Moyer’s RAM receives instructions from
memory cells in the ROM, we agree with Appellant that the proposed
combination does not teach the disputed limitations.
Because Appellant shows at least one reversible error in the
Examiner’s obviousness rejection of independent claim 1, we do not reach
Appellant’s remaining arguments. Accordingly, we do not sustain the
Examiner’s obviousness rejection of independent claim 1. Likewise, we do
not sustain the rejections of claims 2–6, 9–13, 15–18, 20, 23–29, 31–33, and
35–44, which also recite the disputed limitations.
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VI. CONCLUSION
For the above reasons, we reverse the Examiner’s rejections of claims
1–6, 9–13, 15–18, 20, 23–29, 31–33, and 35–44.
VII. DECISION SUMMARY
In summary:
Claim(s)
Rejected
35
U.S.C. § Reference(s)/Basis Affirmed Reversed
1–6, 9, 10,
18, 23–28,
31, 33, 35–
37, 39, 40, 42
103 Hsieh, Moyer
1–6, 9, 10,
18, 23–28,
31, 33, 35–
37, 39, 40, 42
13, 15, 16, 41 103 Hsieh, Iwai 13, 15, 16, 41
29 103 Hsieh, Moyer, Morad 29
11, 20, 32, 38 103 Hsieh, Moyer, Tashiro 11, 20, 32, 38
12 103 Hsieh, Moyer, Dawson 12
17 103 Hsieh, Iwai, Tashiro, Moyer 17
43 Hsieh, Moyer, Iwai 43
44 103 Hsieh, Iwai, Vauclair 44
Overall
Outcome
1–6, 9–13,
15–18, 20,
23–29, 31–
33, 35–44

REVERSED