Mark Boone et al.

Patent Trials and Appeals Board

Aug 2, 2021

2020004178 (P.T.A.B. Aug. 2, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/524,253 06/15/2012 Mark R. Boone P0040448.USU1/LG10126 9783
27581 7590 08/02/2021
Medtronic, Inc. (CVG)
8200 Coral Sea Street NE.
MS: MVC22
MINNEAPOLIS, MN 55112
EXAMINER
IDA, GEOFFREY H
ART UNIT PAPER NUMBER
2892
NOTIFICATION DATE DELIVERY MODE
08/02/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
rs.patents.one@medtronic.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MARK R. BOONE,
MOHSEN ASKARINYA, RANDOLPH E. CRUTCHFIELD,
ERIK J. HERRMANN, MARK S. RICOTTA, and LEJUN WANG
Appeal 2020-004178
Application 13/524,253
Technology Center 2800
Before JAMES C. HOUSEL, GEORGE C. BEST, and JULIA HEANEY,
Administrative Patent Judges.
HOUSEL, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–4, 8–10, 18, 19, and 29. The
Examiner has withdrawn additional pending claims 5, 6, 11–17, and 20–28
from consideration. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies Medtronic, Inc. as the real party in interest. Appeal Brief (“Appeal
Br.”) filed October 18, 2019, 2.
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CLAIMED SUBJECT MATTER
The invention relates to wafer level packages of high voltage (“HV”)
units suitable for use in implantable medical devices, such as implantable
cardiac defibrillators (“ICDs”). Specification (“Spec.”) filed June 15, 2012,
1:19–21.2 Appellant discloses that emerging wafer level packaging
processes (redistributed chip packaging and wire-free die-on-die stack
technology) can facilitate significant downsizing of ICD circuitry such that
the overall size of the device may be reduced to increase implant comfort.
Id. at 2:27–3:4. Appellant discloses that there is still a need for new
combinations of these processes directed toward improved configurations of
wafer level packaging for HV units in ICDs. Id. at 3:5–7.
Claim 1, reproduced below from the Claims Appendix to the Appeal
Brief, illustrates the claimed subject matter. A limitation at issue in this
appeal is italicized.
1. A multi-chip modular wafer level package of a high voltage unit
for an implantable cardiac defibrillator, the package comprising:
a high voltage (HV) component chip including a first
conductive contact surface located on a first side thereof, and a
second conductive contact surface located on a second side
thereof, the second side of the HV chip being opposite the first
side of the HV chip;
an interconnect coupled to the second conductive contact
surface of the HV chip, wherein the interconnect comprises:
an interconnect segment; and
a conductive coupling extending between the
second conductive contact surface of the HV chip to the
interconnect segment to electrically couple the second

2 This Decision also cites to the Final Office Action (“Final Act.”) dated
March 22, 2019, the Examiner’s Answer (“Ans.”) dated March 16, 2020,
and the Reply Brief (“Reply Br.”) filed May 18, 2020.
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conductive contact surface of the HV chip to the
interconnect segment; and
a reconstituted wafer formed by a polymer mold
compound in which the HV chip is encapsulated together with
other chips of the multi-chip modular wafer level package,
wherein the polymer mold compound forming the reconstituted
wafer fully encapsulates the conductive coupling of the
interconnect and encapsulates the HV chip and the other chips
such that the first side of each chip is coplanar with a first side of
the wafer, and wherein the polymer mold compound forming the
reconstituted wafer encapsulates the HV chip and the other chips
such that the second side of the HV chip coupled to the
interconnect is enclosed within the polymer mold compound,
wherein at least a portion of the interconnect coupled to
the second conductive contact surface located on the second side
of the HV chip is encapsulated within the polymer mold
compound used to form the reconstituted wafer and the
interconnect segment provides an interconnect segment contact
surface at the first side of the wafer.
Independent claims 18 and 19 similarly recite multi-chip modular
wafer level packages of an HV unit for an ICD, wherein the packages
comprise conductive couplings that are fully encapsulated by polymer mold
compound.
REFERENCES
The Examiner relies on the following prior art:
Name Reference Date
Farnworth et al.
(“Farnworth”)
US 2001/0002068 A1 May 31, 2001
Kroeninger et al.
(“Kroeninger”)
US 2009/0261468 A1 Oct. 22, 2009
Hedler et al. (“Hedler”) US 2010/0013101 A1 Jan. 21, 2010
Mahler et al. (“Mahler”) US 2010/0148381 A1 June 17, 2010
Wang US 2011/0198638 A1 Aug. 18, 2011

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REJECTIONS
The Examiner maintains, and Appellant requests our review of, the
following rejections under 35 U.S.C. § 103(a):
1. Claims 1, 4, 8, 9, and 29 as unpatentable over Mahler in view of
Kroeninger;
2. Claims 2, 3, and 10 as unpatentable over Mahler in view of
Kroeninger, and further in view of Farnworth;3
3. Claim 18 as unpatentable over Mahler in view of Kroeninger
and Hedler; and
4. Claim 19 as unpatentable over Mahler in view of Kroeninger,
Hedler and Wang.
OPINION
The Examiner finds that Mahler discloses a multi-chip wafer level
package of an HV chip for an ICD substantially as recited in claim 1, except
for encapsulating the HV chip with other chips in a polymer mold compound
for the package. Final Act. 3–4. However, the Examiner finds that
Kroeninger teaches encapsulating an HV chip without other chips in a
polymer mold compound of a multi-chip modular wafer level package. Id. at
4. The Examiner concludes that it would have been obvious to modify
Mahler to encapsulate the HV chip with other chips in a polymer mold
compound in order to reduce device warpage and facilitate further
processing. Id.
With regard to the limitation in claim 1 that the polymer mold
compound fully encapsulates the conductive coupling of the interconnect,

3 The Examiner’s statement for this rejection inadvertently omitted
Farnworth, which is discussed and relied on in the body of this rejection. See
Final Act. 7–8.
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the Examiner provides an annotated drawing, reproduced below, of Mahler’s
Figure 1, showing a cross-sectional view of a semiconductor chip. Final
Act. 5.

Examiner’s Annotated Drawing of Mahler’s Fig. 1,
showing a cross-sectional view of a semiconductor chip

The Examiner finds that Mahler discloses HV chip 224 encapsulated in
polymer mold compound 76, 78, with an interconnect comprising
interconnect segment 82 and conductive coupling 84 extending between
second conductive contact surface 24 to interconnect segment 82. Id. at 3.
The Examiner further finds that “at least a portion of the interconnect 84
coupled to the second conductive contact surface 24 located on the second
side of the chip 22 is encapsulated with the polymer mold compound 78.” Id.
at 4. The Examiner finds that the portion of element 84 corresponds to the
recited conductive coupling of claim 1, such that this boxed portion is fully

4 Throughout this Opinion, for clarity, we present labels to elements in
figures without bold font, regardless of their presentation in the original
document.
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encapsulated in polymer mold compound 78 because it does not extend to
the edge of the package. Id. at 3.
Appellant argues, inter alia, that the Examiner’s interpretation of
Mahler, particularly as shown in the annotated drawing of Figure 1, is
erroneous. Appeal Br. 11–23. Appellant contends that the Examiner’s
designation of the boxed portion of Mahler’s interconnect as corresponding
to the recited conductive coupling is merely an imaginary boundary
unsupported by any teaching or suggestion in Mahler. Id. at 12. Appellant
further contends that Mahler only reasonably suggests that first metal layer
84 and electrically conductive material 82 are a single piece because
Mahler’s drawings show no break or change in materials therebetween. Id. at
14. To the contrary, Appellant urges that Mahler describes manufacturing
processes that would not separate first metal layer 84 from conductive
material 82 by the imaginary boundary selected by the Examiner. Id. at 15.
At most, Appellant urges that these two structures would be separated as
shown in Appellant’s annotated drawing, reproduced below, of Mahler’s
Figure 1.

Appellant’s Annotated Drawing of Mahler’s Fig. 1,
showing a cross-sectional view of a semiconductor chip
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As shown in this annotated drawing, Appellant has boxed a portion of
element 84 such that this element extends to the edge of the package and,
therefore, would not be fully encapsulated in polymer mold compound 78.
Appellant asserts that Mahler’s first disclosed process forms structures 82
and 84 by deposition such that these are either a single piece or element 84 is
a separate layer that extends to the edge of the package as shown in
Appellant’s annotated drawing. Id. at 16–18. Appellant also asserts that
Mahler’s second disclosed process utilizes a metallized adhesive layer 104
(corresponding to first metal layer 84) and separately forms metallized
material 162 over layer 104, which leaves layer 104 as extending to the edge
of the package (corresponding to Appellant’s annotated drawing). Id. at 19–
22.
Appellant’s arguments are persuasive of reversible error. The
Examiner has the initial burden of establishing a prima facie case of
obviousness based on an inherent or explicit disclosure of the claimed
subject matter under 35 U.S.C. § 103. In re Oetiker, 977 F.2d 1443, 1445
(Fed. Cir. 1992) (“[T]he examiner bears the initial burden, on review of the
prior art or on any other ground, of presenting a prima facie case of
unpatentability.”). To establish a prima facie case of obviousness, the
Examiner must show that each and every limitation of the claim is described
or suggested by the prior art or would have been obvious based on the
knowledge of those of ordinary skill in the art. In re Fine, 837 F.2d 1071,
1074 (Fed. Cir. 1988). Here, the Examiner has not established by a
preponderance of the evidence that Mahler’s first metal layer 84 does not
extend to the edge of the package such that it is fully encapsulated in
polymer mold compound as required by claim 1. As such, the Examiner has
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not carried the burden of establishing, by a preponderance of the evidence,
the factual basis for the conclusion that the claimed invention would have
been obvious.
It is well established that “the PTO must give claims their broadest
reasonable construction consistent with the specification. . . . Therefore, we
look to the specification to see if it provides a definition for claim terms, but
otherwise apply a broad interpretation.” In re ICON Health & Fitness, Inc.,
496 F.3d 1374, 1379 (Fed. Cir. 2007). However, “[t]he correct inquiry in
giving a claim term its broadest reasonable interpretation in light of the
specification is not whether the specification proscribes or precludes some
broad reading of the claim term adopted by the examiner. And it is not
simply an interpretation that is not inconsistent with the specification. It is an
interpretation that corresponds with what and how the inventor describes his
invention in the specification, i.e., an interpretation that is consistent with the
specification.” In re Smith Int’l, Inc., 871 F.3d 1375, 1382–83 (Fed. Cir.
2017) (internal quotation omitted).
Although the Examiner is correct that claim 1 broadly recites both the
interconnect segment and conductive coupling, nonetheless claim 1 makes
clear that these are distinct structures. Further, we note that the Specification
describes that the interconnect segments are located on a single side of the
reconstituted wafer which may be part of a preformed lead frame. Spec.
3:22–25. In addition, the interconnect segments have surfaces exposed at a
first side of the package. Id. at 8:8–11; see also, claim 1 (“the interconnect
segment provides an interconnect segment contact surface at the first side of
the wafer”). Conversely, the Specification describes wire bonds or layers of
conductive polymer are formed to electrically couple the HV chip contact
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surface to an interconnect segment. Spec. 3:25–4:1; 7:22–27; 10:12–16; see
also, 11:18–12:10 (conductive polymer 71, redistribution layer 712, and
through polymer via 725). In each instance, the disclosed conductive
couplings are distinct structures, separately formed from the interconnect
segments, such that the couplings are fully encapsulated in the polymer mold
compound.
Further, the Examiner’s interpretation of Mahler’s first metal layer 84
as defining part of the interconnect segment, as well as the conductive
coupling is not consistent with Mahler’s disclosure of how this layer and
conductive material 82 are formed. Mahler describes a first process in which
conductive material 82 and layer 84 are formed sequentially, thereby
suggesting a demarcation between layer 84 and conductive material 82 such
that layer 84 laterally extends to the edge of the package. See Mahler, ¶ 30
(metallized material 42 is deposited into through openings 40, and
metallized material 44 laterally extends over chip 22’s second contact
surface 24), Figs. 3–8. In Mahler’s second process, the conductive coupling
is formed by metallized adhesive layer 104 (which again extends to the
package’s edge) and the interconnect segments are formed over layer 104
between the chips, such that layer 84 again laterally extends to the package’s
edge. Id. ¶¶ 35–37, Figs. 9–18. Thus, an ordinary artisan would have
considered layer 84 as extending to the package’s edge.
We note that the Examiner does not dispute or otherwise respond to
Appellant’s assertions in this regard. Indeed, the Examiner acknowledges
that the interpretation of Mahler’s Figure, and specifically the location of the
conductive coupling and the interconnect segment, is not based on Mahler’s
method teachings. Ans. 5. Thus, it is apparent that the Examiner’s
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interpretation of Mahler’s Figure with regard to the locations of the coupling
and the segment are neither based on Mahler’s teachings, nor on any
reasonable interpretation of Appellant’s disclosure. As such, the Examiner’s
interpretation is unreasonable. Each of the Examiner’s obviousness
rejections is based on this unreasonable interpretation. The Examiner does
not rely on the teachings of Kroeninger, Farnworth, Hedler, or Wang to
remedy this deficiency in Mahler. Accordingly, we do not sustain the
Examiner’s obviousness rejections.
CONCLUSION
Upon consideration of the record and for the reasons set forth above
and in the Appeal and Reply Briefs, the Examiner’s decision to reject claims
under 35 U.S.C. § 103(a) is reversed.
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1, 4, 8, 9, 29 103(a) Mahler, Kroeninger 1, 4, 8, 9, 29
2, 3, 10 103(a) Mahler, Kroeninger,
Farnworth
2, 3, 10
18 103(a) Mahler, Kroeninger,
Hedler
18
19 103(a) Mahler, Kroeninger,
Hedler, Wang
19
Overall
Outcome
1–4, 8–10,
18, 19, 29

REVERSED