LG Display Co., Ltd.

Patent Trials and Appeals Board

Jul 27, 2020

14629538 - (D) (P.T.A.B. Jul. 27, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/629,538 02/24/2015 Youngjang LEE 041501-7184 2084
9629 7590 07/27/2020
Morgan, Lewis & Bockius LLP (WA)
1111 Pennsylvania Avenue, N.W.
Washington, DC 20004
EXAMINER
TRAN, DZUNG
ART UNIT PAPER NUMBER
2829
NOTIFICATION DATE DELIVERY MODE
07/27/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
karen.catalano@morganlewis.com
patents@morganlewis.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
________________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte YOUNGJANG LEE, KYUNGMO SON, SEONGPIL CHO,
JAEHOON PARK, SOHYUNG LEE, SANGSOON NOH,
MOONHO PARK, SUNGJIN LEE,
SEUNGHYO KO, and MIJIN JEONG
________________________

Appeal 2019-004572
Application 14/629,538
Technology Center 2800
________________________

Before N. WHITNEY WILSON, DEBRA L. DENNETT, and
LILAN REN, Administrative Patent Judges.

WILSON, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
August 9, 2018 decision finally rejecting claims 1–8, 10, 12–18, and 22–25.
We have jurisdiction over the appeal under 35 U.S.C. § 6(b). An oral
hearing was held on July 22, 2020, a transcript of which will be made part of
the record.
We AFFIRM IN PART.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies LG Display Co. Ltd. as the real party
in interest. (Appeal Br. 3).
Appeal 2019-004572
Application 14/629,538

2
CLAIMED SUBJECT MATTER
Appellants’ disclosure is directed to a thin film transistor substrate
which can be used for displays with low power consumption (Abstract,
Spec. ¶¶ 8–9). The claimed substrate includes a substrate, a first thin film
transistor (TFT) including a first gate electrode disposed at a first area of the
substrate, and second TFT including a second gate electrode and an oxide
semiconductor layer disposed at a second area of the substrate (Abstract). A
nitride layer is disposed on only the first area of the substrate and covers the
first gate electrode, but not the second gate electrode (id.). The nitride layer
is disposed under an oxide layer which in turn is disposed over the first and
second gate electrodes and under the oxide semiconductor layer (Spec. ¶¶
49, 50, and 52). Details of the claimed invention are set forth in independent
claim 1, which is reproduced below from the Claims Appendix of the
Appeal Brief (with the relevant phrases emphasized):
1. A display, comprising:
a first area;
a second area;
a first thin film transistor disposed at the first area, the first
thin film transistor comprising:
a polycrystalline semiconductor layer;
a first gate electrode on the polycrystalline
semiconductor layer;
a first source electrode; and
a first drain electrode;
a second thin film transistor disposed at the second area, the
second thin film transistor comprising:
Appeal 2019-004572
Application 14/629,538

3
a second gate electrode;
an oxide semiconductor layer on the second gate
electrode;
a second source electrode; and
a second drain electrode;
a nitride layer disposed at only the first area, the nitride
layer covering the first gate electrode, without covering the
second gate electrode; and
an oxide layer disposed:
over the first gate electrode and the second gate
electrode;
directly on and contacting the nitride layer in the first
area; and
directly under and contacting the oxide semiconductor
layer in the second area
wherein the nitride layer is disposed between the first gate
electrode and the oxide layer in the first area.

REJECTIONS
I. Claims 1, 3, 4, 7, 8, 10, 12, 17, 18, and 20 are provisionally
rejected on the grounds of nonstatutory double patenting over claims 1–7, 9,
and 10 of the ’357 Application.2

2 US Application No. 14/628,357. The ’357 Application has matured into
US Patent No. 10,186,528 (issued January 22, 2019). It does not appear that
the claims were amended between the time of the Final Action in the case on
appeal and issuance of the ’528 Patent. Accordingly, while the rejection is
Appeal 2019-004572
Application 14/629,538

4
II. Claims 2 and 5 are provisionally rejected on the ground of
nonstatutory double patenting over claim 1 of the ’357 Application in view
of Yan.3, 4
III. Claim 6 is provisionally rejected on the ground of nonstatutory
double patenting over claim 1 of the ’357 Application in view of Lee.5, 6
IV. Claims 1–5, 7–10, 12–15, 17–20, 22, and 23–257 are rejected
under 35 U.S.C. § 103 as unpatentable over Kimura,8 in view of Yang,9 as
evidenced by Yamada.10
V. Claims 8, 10, 18, and 20 are rejected under 35 U.S.C. § 103 as
unpatentable over Kimura and Yang, and further in view of Isobe.11
VI. Claims 6 and 16 are rejected under 35 U.S.C. § 103 as
unpatentable over Kimura and Yang, and further in view of Lee.

DISCUSSION
Rejections I, II, and III. Appellant argues all of these rejections as a
group (Appeal Br. 12). Accordingly, we select claim 1 as representative and

denoted in the Final Action as “provisional,” we will address the arguments
on the merits as though it had been made over the issued patent.
3 See Footnote 2, supra.
4 Yan et al., US 2013/0168666 A1, published July 4, 2013.
5 See Footnote 2, supra.
6 Lee, US 2004/0075783 A1, published April 22, 2004.
7 Claims 24 and 25 are not specifically recited in the recitation of the
rejection (Final Act. 12), but are enumerated in discussing the rejection
(Final Act. 20) and are, therefore, presumed to be subject to this rejection.
8 Kimura, US 2010/0193785 A1, published August 5, 2010.
9 Yang et al., US 2013/0015448 A1, published January 17, 2013.
10 Yamada et al., US 2004/0016924 A1, published January 29, 2004.
11 Isobe et al., US 2006/0246644 A1, published November 2, 2006.
Appeal 2019-004572
Application 14/629,538

5
will focus our discussion on the double patenting rejection of claim 1. Our
analysis will apply to each of the claims subject to these rejections.
Appellant focuses on the following limitation of claim 1 as
representing the difference between the claims on appeal and the claims of
the ‘357 Application: “an oxide layer disposed . . . directly on and
contacting the nitride layer in the first area; and directly under and
contacting the oxide semiconductor layer in the second area.” In particular,
Appellant argues that the claims of the ‘357 Application do not recite that
the nitride layer is in contact with the oxide layer and the oxide
semiconductor layer, and that the Examiner has not provided an explanation
on why that difference is not patentably distinct (Appeal Br. 10–11).
The judicial doctrine of obviousness-type double patenting precludes
an applicant from extending the term of protection for a patented invention
by claiming an obvious variant of the patented invention in a subsequent
patent application. See In re Longi, 759 F.2d 889, 892 (Fed. Cir. 1985). In
determining whether the claim 1 of the application on appeal is an obvious
variant over claim 1 of the ‘357 Application, it is appropriate to review the
Specification of the ‘357 Application in order to understand the scope of its
claim 1. Eli Lilly & Co. v. Teva Parenteral Medicines, Inc., 689 F.3d 1368,
1378‒79 (Fed. Cir. 2012)
The Examiner finds that the Specification of the ‘357 Application
specifically states that the oxide layer is in direct contact with the nitride
layer (Ans. 3–4). Thus, the proper construction of the phrase “under the
oxide layer” as used in claim 1 of the ‘357 Application would include “an
oxide layer disposed . . . directly on and contacting the nitride layer” as used
in claim 1 on appeal. In other words, claim 1 on appeal is somewhat
Appeal 2019-004572
Application 14/629,538

6
narrower than claim 1 of the ‘357 Application, but is clearly covered by it.
The Examiner determines that the difference in scope between the claims is
not of patentable significance. Appellant has not provided an explanation of
why that determination is reversibly erroneous.
Accordingly, we determine that Appellant has not demonstrated
reversible error in the nonstatutory double patenting rejections. Should
prosecution resume, the Examiner will wish to consider whether the
provisional rejections should be made non-provisional in light of the
issuance of the ‘357 Application as US Patent No. 10,186,528.
Rejections IV, V, and VI. Appellant argues all of the claims together
(see, Appeal Br. 21), so we will focus our analysis on the rejection of claim
1. The remaining claims will stand or fall with claim 1.
Appellant presents two general arguments seeking reversal of the
prior art rejections. We address each in turn.
Argument 1. The Examiner finds, with reference to FIG. 6,
that Kimura discloses “an oxide layer (Fig. 6, (201); [0160] that is disposed
(a) over the first gate electrode (104A) and the second gate electrode,” (b)
“directly on and contracting the nitride layer in the first area,” and (c)
“directly under and contacting the oxide semiconductor layer 202(a) in the
second area” (Final Act. 13):
Appeal 2019-004572
Application 14/629,538

7

Kimura’s FIG. 6 illustrates a manufacturing step of a semiconductor device.

The Examiner further finds that Kimura’s insulating layer 201 is a
stacked-layer which contains both silicon oxide and silicon nitride layers and
that, based on Yamada, it appears that the silicon nitride layer is under the
oxide layer, allowing the oxide layer to contact the oxide semiconductor
layer 202(A) (Final Act. 13). The Examiner’s finding is supported by the
following excerpt from Kimura:
[160] The insulating layer 201 can be formed by a single
layer structure or a stacked-layer structure of a siloxane
resin; a film, of silicon oxide (SiOx), silicon nitride (SiNx),
silicon oxynitride (SiOxNy) (x>y), silicon nitride oxide
(SiNxOy) (x>y), or the like; a film containing carbon, such as a
DLC (diamond-like carbon); an organic material such as
epoxy, polyimide, polyamide, polyvinyl phenol,
benzocyclobutene, or acrylic; or an insulating film containing
oxygen or nitrogen. Note that a siloxane resin corresponds to a
resin having Si–O–Si bonds. Siloxane includes a skeleton
structure of a bond of silicon (Si) and oxygen (O). As a
substituent, an organic group containing at least hydrogen
(such as an alkyl group or aromatic hydrocarbon) is used.
Alternatively, a fluoro group, or a fluoro group and an organic
group containing at least hydrogen can be used as a
substituent.

[0161] It is preferable that a portion of the insulating layer 201
in contact with a semiconductor layer 202, which is provided
Appeal 2019-004572
Application 14/629,538

8
later, be silicon nitride (SiNx). The semiconductor layer 202
includes hydrogen in some case. In that case, reacting the
hydrogen included in the semiconductor layer 202 and the
insulating layer 201 can be prevented by using silicon nitride
(SiNx) as the insulating layer 201.

(Kimura, ¶¶ 160, 161, emphasis added).
Appellant points (Appeal Br. 16) to the first sentence in paragraph 161
as evidence that Kimura does not teach that the oxide layer is on top of the
nitride layer, because it suggests a preference for having the top layer (in
contact with the semiconductor layer) be silicon nitride: “It is preferable
that a portion of the insulating layer 201 in contact with a semiconductor
layer 202, which is provided later, be silicon nitride (SiNx)” (Kimura, ¶ 161).
This argument is not persuasive, because although Kimura states a
preference for having the nitride layer be the top sublayer in the insulating
layer 201 (which would be outside the scope of claim 1), by indicating that
this is the preferred arrangement, it clearly suggests the arrangement relied
on by the Examiner in the rejection, where the nitride layer is under the
oxide layer, as recited in the claim. A reference is not limited to its preferred
embodiment, but must be evaluated for all of its teachings, including its
teachings of non-preferred embodiments. See In re Burckel, 592 F.2d 1175,
1179 (CCPA 1979).
Argument 2. Appellant’s second argument is that none of the
applied references, either alone or in combination, suggests or otherwise
renders obvious the nitride layer that is on only the first area of the substrate,
covering the first gate electrode without covering the second gate electrode,
and has specific spatial relationships with the other layers (i.e. disposed
Appeal 2019-004572
Application 14/629,538

9
under the oxide layer, which in turn is disposed under the oxide
semiconductor layer) (Appeal Br. 18–19).
The Examiner, finding that this limitation is not taught by Kimura,
relies on Yang to teach this element, finding that Yang teaches a nitride
layer 222 disposed on only the first area of the display 101 without covering
the second gate electrode 142, as shown in FIG. 13:

FIG. 13 is a schematic diagram illustrating a semiconductor device and a
fabrication method thereof according an embodiment of Yang.

The Examiner concludes that:
It would have been obvious to a person of ordinary skill in the
art before the effective filing date of the invention to modify
claim 1 of Kimura '785 as taught by Yang '448 to have a nitride
layer disposed on only the first area of the display, the nitride
layer covering the first gate electrode, without covering the
second gate electrode in order to provide nitride layer over the
first channel layer composed of polycrystalline silicon to obtain
Appeal 2019-004572
Application 14/629,538

10
a top gate type thin film transistor having improved
characteristics (as evidenced by Yamada '924, see Abstract,
para. [0012]-[0016]) and to diminish hydrogenation of the
second channel layer composed of oxide semiconductor,
thereby ensuring semiconductor property of the second channel
layer, and thus protecting the semiconductor properties of the
second channel layer (see para. [0037]) to obtain a
semiconductor device with advanced electrical performance
(see para. [0007]-[0009]).

(Final Act. 13–14).
Appellant argues (Appeal Br. 19) that Kimura teaches away from the
claimed arrangement where the nitride layer is not present in the second
region and over the second gate electrode because Kimura states a
preference for having the nitride layer in contact with the oxide
semiconductor layer, in order to prevent reacting the hydrogen included in
the semiconductor layer 202 and the insulating layer (Kimura ¶ 161). Yang
teaches precisely the opposite, explaining why a person of skill in the art
might have sought to avoid having the nitride layer in the same region as the
oxide semiconductor layer in order to prevent the tendency of hydrogen
atoms to diffuse to the second channel layer 20 during formation of the
second interlayered dielectric layer 222 and ensuring the semiconductor
property of the second channel layer 20 (Yang ¶ 37).
The Examiner has not adequately explained why a person of skill in
the art would have credited Yang’s teaching over Kimura’s teaching in order
to modify Kimura’s structure. In other words, while the Examiner has
shown that Yang might offer, in a vacuum, some rationale to modify
Kimura’s structure as needed to meet the claim limitations, Kimura itself
expressly rejects that reasoning. The Examiner has not explained why a
Appeal 2019-004572
Application 14/629,538

11
person of skill in the art would reject Kimura’s teachings in favor of Yang in
order to modify Kimura’s structure. Accordingly, we reverse the rejection.
Moreover, because the limitation in question is common to each of the
claims, we also reverse the prior art rejections for all of the claims.

Appeal 2019-004572
Application 14/629,538

12
CONCLUSION
In summary:

Claims
Rejected
Grounds/35
U.S.C. §
Reference(s)/Basis Affirmed Reversed
1, 3, 4, 7, 8,
10, 12, 17,
18, 20
Nonstatutory
double
patenting
US Application
14/628,357
1, 3, 4, 7,
8, 10, 12,
17, 18, 20

2, 5 Nonstatutory
double
patenting
US Application
14/628,357, Yan
2, 5
6 Nonstatutory
double
patenting
US Application
14/628,357, Lee
6
1–5, 7–10,
12–15, 17–
20, 22–25
103 Kimura, Yang,
Yamada
1–5, 7–10,
12–15,
17–20,
22–25
8, 10, 18,
20
103 Kimura, Yang,
Yamada, Isobe
8, 10, 18,
20
6, 16 103 Kimura, Yang,
Yamada, Lee
6, 16
Overall
Outcome
1–8, 10,
12, 17, 18,
20
13–16,
22–25

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED IN PART