Lantiq Beteiligungs-GmbH & Co. KG

Patent Trials and Appeals Board

Oct 1, 2021

2020003282 (P.T.A.B. Oct. 1, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/527,138 05/16/2017 Ritesh Banerjee LP1966PC00-
US_INT200605WO
6813
148528 7590 10/01/2021
2SPL Patent Attorneys
Intel Filings
Landaubogen 3
Munich, 81373
GERMANY
EXAMINER
WADDY JR, EDWARD
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
10/01/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
mail@2spl.de
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte RITESH BANERJEE, JIAXIANG SHI, and
INGO VOLKENING
_______________

Appeal 2020-003282
Application 15/527,1381
Technology Center 2100
_______________

Before MICHAEL J. STRAUSS, HUNG H. BUI, and
ADAM PYONIN, Administrative Patent Judges.

BUI, Administrative Patent Judge.

DECISION ON REQUEST FOR REHEARING
Appellant filed a Request for Rehearing under 37 C.F.R. § 41.52(b)(2)
for reconsideration of our Decision on Appeal, mailed July 19, 2021
(“Decision”). In that Decision, we issued a new ground of rejection of
claims 14 and 19 under 35 U.S.C. § 103 as obvious over Tamura et al. (US
2005/0138232 A1; published June 23, 2005; “Tamura”). We have
considered Appellant’s new arguments presented in the Request for
Rehearing (“Req. Reh’g”), but we are not persuaded by Appellant’s
arguments. We have provided herein additional explanations, but decline to
change our decision in view of Appellant’s arguments.

1 We use the word “Appellant” to refer to “applicant(s)” as defined in 37
C.F.R. § 1.42. According to Appellant, the real party in interest is Lantiq
Beleiligungs-GmbH. Appeal Br. 1.
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Application 15/527,138

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ANALYSIS
The applicable standard for a Request for Rehearing is set forth in
37 C.F.R. § 41.52(b)(2), which provides in relevant part, “[t]he request for
rehearing must address any new ground of rejection and state with
particularity the points believed to have been misapprehended or overlooked
in entering the new ground of rejection and also state all other grounds upon
which rehearing is sought.”
Appellant requests a rehearing regarding Tamura’s DMA controller
106, shown in Figure 1, believed to have been misapprehended or
overlooked in entering the new ground of rejection. Req. Reh’g 2–5. Figure
1 is reproduced below with additional markings for illustration.

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Figure 1 shows a cache memory system having DMA controller 106 for
controlling data access to cache memory 102 and main memory 104.
In particular, Appellant raises two new principal arguments against
the application of Tamura. First, Appellant acknowledges Tamura’s DMA
controller 106, shown in Figure 1, is configured to access to main memory
104, but argues that “DMA controller 106 in Tamura does not access data in
the cache memory” as recited in claims 14 and 19. Req. Reh’g 3.
According to Appellant,
“Tamura merely discloses purging data in the cache memory in
case of inconsistency between the main memory and the cache
memory. Tamura merely teaches deleting the inconsistent data
in the cache memory.”

Id. at 5.
We are not persuaded by Appellant’s argument because Tamura’s
“purging data in the cache memory” necessarily requires “access” to the
“data in the cache memory” as recited in claims 14 and 19.
Second, Appellant also argues because Tamura’s DMA controller 106
purges data in cache memory 102, via purging means 108, “Tamura fails to
teach that the DMA controller 106 is configured to read and write data
between the cache memory and the main memory (i.e., transfer data between
the cache memory and the main memory).” Id. at 4.
We remain unpersuaded. A patent claim is obvious under 35 U.S.C.
§ 103 if the differences between the claimed subject matter and the prior art
are such that the subject matter, as a whole, would have been obvious at the
time the invention was made to a person having ordinary skill in the art to
which said subject matter pertains. KSR Int'l Co. v. Teleflex Inc., 550 U.S.
398, 406 (2007). “[H]owever, the analysis need not seek out precise
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teachings directed to the specific subject matter of the challenged claim, for
a court can take account of the inferences and creative steps that a person of
ordinary skill in the art would employ.” Id. at 418; see also In re Preda, 401
F.2d 825, 826 (CCPA 1968) (“[I]n considering the disclosure of a reference,
it is proper to take into account not only specific teachings of the reference
but also the inferences which one skilled in the art would reasonably be
expected to draw therefrom.”). In this regard, “[a] person of ordinary skill is
also a person of ordinary creativity, not an automaton.” KSR, 550 U.S. at
421. Moreover,
[w]hen there is a design need or market pressure to solve a
problem and there are a finite number of identified, predictable
solutions, a person of ordinary skill has good reason to pursue
the known options within his or her technical grasp. If this leads
to the anticipated success, it is likely the product not of
innovation but of ordinary skill and common sense. In that
instance the fact that a combination was obvious to try might
show that it was obvious under § 103.
Id. at 421 (underlining added).
As previously explained, Tamura’s DMA controller 106, shown in
Figure 1, is configured to access data in cache memory 102 as well as data in
main memory 104. Tamura’s Figure 1 shows (1) a direct line from DMA
controller 106 to main memory 104 and (2) an indirect line from DMA
controller 106 to cache memory 102, via purge means 108. Tamura ¶¶ 2, 5,
7, 10–16, 30.
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Likewise, Tamura’s Figure 10 further depicts data in main memory
104 and data in cache memory 102, as reproduced below:

Figure 10 shows the relationship between data in main memory 104 and data
in cache memory 102, where a part of data in main memory 104 is stored in
cache memory 102, where either a CPU or a dedicated address control
means such as, for example, Tamura’s DMA controller 106 is used to access
and transfer data from main memory 104 to cache memory 102. Tamura ¶¶
4–5.
As its name implies, DMA (Direct Memory Access) is a feature of
computer systems that allows directly access to memory independently of
the CPU. Tamura ¶ 7. As is well known to those ordinary skilled artisans in
computer architectures, DMA controller can directly access memory (e.g.,
main memory, cache memory or I/O memory) and is used to transfer data
from one memory location to another, as evidenced in the prior art of record,
including, for example: Bartley’s Figure 1, ¶¶ 2–6, 23 (US 2007/0083682
A1; published Apr. 12, 2007; “Bartley”), Tamura’s Figure 10, ¶¶ 4–16, as
well as widely distributed information available at
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https://en.wikipedia.org/wiki/Direct_memory_access.
As recognized by Appellant, Tamura’s disclosure focuses on purging
data in cache memory 102 whenever the DMA transfer data to main memory
104 reaches a set threshold value to prevent data inconsistency. Req. Reh’g
4–5. As such, Tamura does not and need not expressly describe data transfer
between main memory 104 and cache memory 102, shown in Figure 1.
Nevertheless, there are only a finite identified, predictable mechanisms
available to control the data transfer between main memory 104 and cache
memory 102, including, for example, a CPU or a DMA controller.
Given the teachings of Tamura’s Figures 1 and 10 and the well-
established functions of a DMA controller, we find the use of Tamura’s
DMA controller 106 to read and write data between main memory 104 and
cache memory 102 or transfer data between these memory components
would have been obvious to those ordinarily skilled artisans. For example,
those ordinarily skilled artisans, looking at Tamura’s Figure 1 and Figure 10
and the well-established functions of a DMA controller, would draw a
reasonable inference that Tamura’s DMA controller 106 would be able to
access data in main memory 104 and data in cache memory 102 as well as to
transfer data between main memory 104 and cache memory 102
independently of the CPU.

CONCLUSION
We have considered the new arguments raised by Appellant in the
Request, but find none of these arguments persuasive that our original
Decision misapprehended or overlooked in entering the new ground of
rejection. It is our view, Appellant has not identified any points the Board
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misapprehended or overlooked. We decline to grant the relief requested.
This Decision on Appellants’ “REQUEST FOR REHEARING” is deemed
to incorporate our earlier Decision by reference. See 37 C.F.R.
§ 41.52(a)(1).

DECISION
We have granted Appellant’s request to the extent that we have
reconsidered our Decision, but we deny the request with respect to making
any changes therein. The new ground of rejection of claims 14 and 19 under
35 U.S.C. § 103 as obvious over Tamura remains AFFIRMED.

REHEARING DENIED
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Outcome of Decision on Rehearing:

Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Granted Denied
14, 19 103 Tamura 14, 19
Overall
Outcome
14, 19

Final Outcome of Appeal After Rehearing

Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed New
Grounds
14–28,
30
103 Adiraju, Batley,
Tamura
27, 28, 30 14–26
14, 19 103 Tamura 14, 19 14, 19
Overall
Outcome
27, 28, 30 14–26 14, 19