Lantiq Beteiligungs-GmbH & Co. KG

Patent Trials and Appeals Board

Jul 19, 2021

2020003282 (P.T.A.B. Jul. 19, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/527,138 05/16/2017 Ritesh Banerjee LP1966PC00-
US_INT200605WO
6813
148528 7590 07/19/2021
2SPL
Patent Attorneys
Landaubogen 3
Munich, 81373
GERMANY
EXAMINER
WADDY JR, EDWARD
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
07/19/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
Inteldocs_docketing@cpaglobal.com
mail@2spl.de
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
_______________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________

Ex parte RITESH BANERJEE, JIAXIANG SHI, and
INGO VOLKENING
_______________

Appeal 2020-003282
Application 15/527,1381
Technology Center 2100
_______________

Before MICHAEL J. STRAUSS, HUNG H. BUI, and
ADAM PYONIN, Administrative Patent Judges.

BUI, Administrative Patent Judge.

DECISION ON APPEAL
Appellant seeks our review under 35 U.S.C. § 134(a) from the
Examiner’s Final Rejection of claims 14–28 and 30, which are all the claims
pending in the application. We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM-IN-PART.2 Pursuant to our authority under 37 C.F.R.
§ 41.50(b), we enter a new ground of rejection for independent claims 14
and 19.

1 We use the word “Appellant” to refer to “applicant(s)” as defined in 37
C.F.R. § 1.42. According to Appellant, the real party in interest is Lantiq
Beleiligungs-GmbH. Appeal Br. 1.
2 Our Decision refers to Appellant’s Appeal Brief filed August 26, 2019
(“Appeal Br.”); Reply Brief filed March 30, 2020 (“Reply Br.”); Examiner’s
Answer mailed January 29, 2020 (“Ans.”); Final Office Action mailed
February 7, 2019 (“Final Act.”); and original Specification filed May 16,
2017 (“Spec.”).
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STATEMENT OF THE CASE
Appellants’ Invention
According to Appellants, “conventional systems processors may not
be able to perform other tasks, e.g., executing instructions, while accessing a
memory.” Spec. 1:13–14. Appellants’ invention proposes “improved
memory devices, memory management systems [shown in Figure 1] and
associated methods which may for example reduce the burden for a
processor regarding memory operations.” Spec. 2:4–7.
Appellants’ Figure 1 is reproduced below with additional markings
for illustration.

Figure 1 shows computing module (10) utilizing memory copy engine (19)
configured to, independently of CPU (21, 26), read and write data between
cache memory (24, 28) and main memory (16), via DMA port (55).
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According to Appellant, “[t]his manner of memory copy has an
advantage of not hogging CPU time. The HWMemCopy engine 19
especially improves networking throughput and maximizes application
performance for embedded CPU.” Spec. 13:30–33.
Representative Claim
Claims 14, 19, and 27 are independent. Representative claim 14 is
reproduced below:
14. A memory module for a computing device having a
central processing unit (CPU), the memory module comprising:
a main memory,
at least one cache memory configured to store copies of
frequently used data of the main memory, and
a memory copy device being connected with the main
memory and with the cache memory,
wherein the memory copy device comprises at least one
Direct Memory Access (DMA) port for accessing data in the
main memory and data in the cache memory, the memory copy
device being configured to, independently of the CPU, read and
write data between the cache memory and the main memory via
the DMA port.

Appeal Br. 11 (Claims App.).
Examiner’s Rejection and References
Claims 14–28 and 30 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Adiraju et al. (US 2009/0055611 A1; published Feb. 26,
2009; “Adiraju”), Bartley et al. (US 2007/0083682 A1; published Apr. 12,
2007; “Bartley”), and Tamura et al. (US 2005/0138232 A1; published June
23, 2005; “Tamura”). Final Act. 3–18.
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ANALYSIS
Claims 14–26
In support of the rejection of independent claim 14, and similarly,
claim 19, the Examiner finds Adiraju teaches most aspects of Appellants’
claimed “memory module,” shown in Figure 1, including a CPU [126], a
main memory [128], a cache memory (i.e., a non-volatile RAM (NVRAM)
138), and a memory copy device connected with the main memory and the
cache memory (i.e., a NVRAM management unit 136). Final Act. 3–7
(citing Adiraju’s Figure 1, ¶¶ 11–13, and 19). To support the conclusion of
obviousness, the Examiner relies on (1) Bartley for teaching the use of
“Direct Memory Access (DMA) port for accessing data in the main memory
and data in the cache memory, independently of the CPU, [to] read and write
data” (id. at 7–8 (citing Bartley ¶ 23, Fig. 1)); and (2) Tamura for teaching
the cache memory “configured to store copies of frequency used data of the
main memory” (id. at 8 (citing Tamura ¶ 5)).
First, Appellant disputes the Examiner’s factual findings regarding
Adiraju. In particular, Appellant argues Adiraju’s NVRAM 136, shown in
Figure 1, is not Appellant’s claimed “cache memory” because the claimed
“cache memory” “is volatile memory, and typically an SRAM that facilitates
very fast reading and writing thereto,” whereas Adiraju’s NVRAM 136,
shown in Figure 1, is a non-volatile RAM used to store critical data “to
maintain a player’s game state in the [event] of a sudden power failure or
upon a change when the NVRAM gets reformatted and such critical data
gets erased.” Appeal Br. 5 (citing Adiraju’s Fig. 1, ¶¶ 11, 18; and
en.wikipedia.org/wiki/CPU_cache).
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Second, Appellant argues the Examiner’s proposed modification of
Adiraju to incorporate Bartley would render Adiraju unsatisfactory for its
intended purpose. Appeal Br. 4–7; Reply Br. 2–5. According to Appellant,
[Adiraju’s purpose] is to ensure game integrity by copying
critical data from an NVRAM to a temporary storage device
when a triggering event occurs (i.e., change in user) so that the
critical data is saved elsewhere prior to another user reformatting
the NVRAM, causing such critical data to be lost. Further,
determination of such trigger is ascertained and then executed via
the CPU 126.
Appeal Br. 6 (emphasis omitted).
Appellant argues “[a] modification of Adiraju et al. in view of Bartley
et al. to add a memory copy device with a DMA port would require the
CPU to be displaced functionally as the entire purpose of DMA is to
bypass the CPU and directly transfer data so that the CPU can be employed
for other tasks” and “[b]ypassing the CPU, however, in Adiraju et al. then
precludes the modified system of ever knowing when the change in user is
occurring and thus the mechanism by which the data transfer occurs is
never initiated.” Appeal Br. 6; Reply Br. 2–4.
Third, because of the differences between Adiraju and Bartley,
Appellant also argues there is no reason or motivation to incorporate the
DMA functionality of Bartley or the cache memory of Tamura into
Adiraju’s control system 106, shown in Figure 1, for managing contents of a
NVRAM in a wagering game machine in order to arrive at Appellants’
claimed invention. Appeal Br. 7–10; Reply Br. 5.
In response, the Examiner maintains the position that “the prior art of
record efficiently reads on the claim limitations based on the current claim
language.” Ans. 22–23. The Examiner also “maintains the motivation to
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combine . . . with Tamura explicitly teaching the high speed data transfer of
which Adiraju may be improved with the use of faster storage and/or
retrieval of said critical data.” Id. at 27.
We are persuaded by Appellant’s arguments and disagree with the
Examiner’s position. Obviousness is a question of law based on underlying
factual findings, In re Baxter, 678 F.3d 1357, 1361 (Fed. Cir. 2012),
including what a reference teaches, In re Beattie, 974 F.2d 1309, 1311 (Fed.
Cir. 1992), and the existence of a reason to combine references, In re Hyon,
679 F.3d 1363, 1365–66 (Fed. Cir. 2012). At the outset, we agree with
Appellant that Adiraju’s NVRAM 136, shown in Figure 1, is a non-volatile
RAM used to store critical data “to maintain a player’s game state in the
[event] of a sudden power failure or upon a change when the NVRAM gets
reformatted and such critical data gets erased” and, as such, is not the same
as Appellant’s claimed “cache memory.” Appeal Br. 5 (citing Adiraju’s Fig.
1, ¶¶ 11, 18; and en.wikipedia.org/wiki/CPU_cache); also see Adiraju ¶ 6
(“Critical data may include one or more of game outcome, credit balance,
reel positions, game history, random number generator seeds, game
configuration, machine configuration, player information, or other state
information or information critical to the operation and record keeping in a
gaming machine”).
As recognized by Appellant, Adiraju teaches a control system 106 for
managing the contents of NVRAM in a wagering game machine, shown in
Figure 1, as reproduced below, with additional markings for illustration.
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Adiraju’s Figure 1 shows control system 106 for managing contents of
NVRAM 138 in wager game machine 100.

NVRAM management unit 136, as shown in Adiraju’s Figure 4, is
configured to initialize and run executable code stored main memory 128 to
copy contents of NVRAM 138 to a temporary storage device (i.e., a
removable media, such as a universal serial bus (USB) memory stick or a
hot-swappable hard drive) at step 302, clear the NVRAM 138 at step 304,
and/or copy data to the NVRAM 138 at step 306. See Adiraju’s ¶¶ 23–24.
However, Adiraju’s NVRAM management unit 136 is not the same as
Appellant’s claimed “memory copy device connected with the main memory
and the cache memory” and “configured to, independently of the CPU, read
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and write data between the cache memory and the main memory” in the
manner recited in Appellant’s claims 14 and 19.
Neither Bartley nor Tamura cure the deficiencies of Adiraju in order
to arrive at Appellant’s claims 14 and 19. Moreover, we also note the
Examiner’s rationale to incorporate the teachings of Bartley and Tamura into
Adiraju is without any “rational underpinning” as required by KSR Int’l Co.
v. Teleflex, Inc., 550 U.S. 398, 418 (2007); and In re Kahn, 441 F.3d 977,
988 (Fed Cir. 2006) (“[R]ejections on obviousness grounds cannot be
sustained by mere conclusory statements; instead, there must be some
articulated reasoning with some rational underpinning to support the legal
conclusion of obviousness.”). For example, the Examiner reasons “[i]t
would have been obvious . . . to improve a system by providing for the
ability of a ‘page copy mechanism . . . that allows DMA operations during a
copy of a memory page.’” Final Act. 8. However, as recognized by
Appellant, “add[ing] a memory copy device with a DMA port would require
the CPU to be displaced functionally as the entire purpose of DAM is to
bypass the CPU and directly transfer data so that the CPU can be employed
for other tasks.” Appeal Br. 6 (emphasis omitted). As such, we are not
persuaded that the Examiner’s rationale for combining Bartley and Adiraju
in the manner suggested by the Examiner is supported by “rational
underpinnings.”
For these reasons, we decline to sustain the Examiner’s obviousness
rejection of independent claims 14 and 19, and their respective dependent
claims 15–18 and 20–26.

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Claims 27, 28, and 30
Independent method claim 27 is significantly broader than claims 14
and 19 because all the hardware components of Appellant’s “memory
module” are recited in its preamble and the claimed method is equipped with
only two basic steps of (1) “translating, in a hardware device, between a
memory physical address and memory virtual address” and (2) “in the
hardware device, reading and writing data between the cache memory and
the main memory via Direct Memory Access.”
On appeal, Appellant bears the burden to demonstrate error in the
Examiner’s position. See In re Kahn, 441 F.3d 977, 985–86 (Fed. Cir.
2006). The Board will not reach the merits of any issues not contested by
Appellant and treat such arguments as waived. See Ex parte Frye, 94
USPQ2d 1072, 1075 (BPAI 2010) (precedential).
In this case, Appellant does not present separate arguments for
patentability of claim 27 and fails to demonstrate why the Examiner’s
findings with respect to claim 27 are in error. We note that Tamura’s
memory system control method, as shown in Figure 1, has all the basic
hardware components recited in Appellant’s claim 27, including a CPU 101,
a cache memory 102, a main memory 104, a DMA controller 106 to read
and write data between the cache memory 102 and the main memory 104,
via DMA, and an address control means 107 for updating or translating
addresses of data written. Tamura ¶¶ 7, 10–16. We also note that Bartley’s
memory controller 180, shown in Figure 1, perform “the virtual-to-physical
address mapping” or translation.” Bartley ¶ 23.
Nevertheless, the preamble of Appellants’ claim 27 is not limiting
because the recited hardware components are not essential structures and do
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not “give life, meaning, and vitality” to the claims. Catalina Marketing
International, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir.
2002).
For the foregoing reasons, we find no reversible error in the
Examiner’s position and, as such, sustain the Examiner’s obviousness
rejection of claim 27 and its dependent claims 28 and 30.

NEW GROUND OF REJECTION
New §103 Rejection of Claims 14 and 19 under 37 C.F.R. § 41.50(b)
Pursuant to our authority under 37 C.F.R. §41.50(b), however, we
reject claims 14 and 19 under 35 U.S.C. § 103 as being unpatentable over
Tamura for the following reasons.
Tamura’s cache memory system equipped with all the claimed
elements of Appellant’s claims 14 and 19, shown in Figure 1, as reproduced
below with additional markings for illustration.
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Figure 1 shows a cache memory system having DMA controller 106 for
performing a DMA control to cache memory 102 and main memory 104.

As shown in Figure 1, Tamura’s cache memory system includes: (1)
CPU 101, (2) main memory 104, (3) cache memory 102 to store data
frequently used from main memory 104, and (4) memory copy device in the
context of a DMA controller 106 for accessing data in the main memory 104
and data in the cache memory 102, and configured to, independently of the
CPU 101, read and write data between the cache memory 102 and the main
memory 106 via the DMA. Tamura ¶¶ 7, 10–16.
Tamura does not expressly describe that the DMA controller 106 is
equipped with at least one DMA port in order to access data in the cache
memory 102 and main memory 104. However, the use of DMA port is
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inherent within Tamura’s DMA controller 106, or alternatively, is well
known by a person skilled in the art to perform a DMA transfer during a data
write operation or a data read operation. As such, we find that a person
skilled in the art, looking at Tamura, would draw a reasonable inference that
the DMA port would be necessarily required for transferring data between
the cache memory 102 and the main memory 104.
For these reasons, we conclude that claims 14 and 19 are unpatentable
under 35 U.S.C. § 103 over Tamura.
The Patent Trial and Appeal Board (PTAB) is a review body rather
than a place of initial examination. We have made the rejection regarding
independent claims 14 and 19 under 37 C.F.R. § 41.50(b). However, we
have not reviewed the remaining claims 15–18 and 20–26 for patentability
over Tamura. We leave the patentability determination with respect to these
dependent claims to the Examiner once the rejection of Appellant’s
independent claims 14 and 19 under 35 U.S.C. § 103 is addressed. See
MPEP §1213.02.

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DECISION
As such, we REVERSE the Examiner’s final rejection of claims 14–
26 as being unpatentable under 35 U.S.C. § 103 over Adiraju, Bartley, and
Tamura. However, we AFFIRM the Examiner’s final rejections of claims
27, 28, and 30 as being unpatentable under 35 U.S.C. § 103 over Adiraju,
Bartley, and Tamura. In addition, pursuant to our authority under 37 C.F.R.
§ 41.50(b), we enter a NEW GROUND of rejection for claims 14 and 19 as
being unpatentable under 35 U.S.C. § 103 over Tamura alone.

DECISION SUMMARY
In summary:
Claims
Rejected
35
U.S.C.
§
Reference(s)
/
Basis
Affirmed Reversed New
Ground
s
14–28,
30
103 Adiraju,
Bartley,
Tamura
27, 28, 30 14–26
14, 19 103 Tamura 14, 19
Overall
Outcome
27, 28,
30

14–26 14, 19

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Rule 37 C.F.R. § 41.50(b) states that “[a] new ground of rejection
pursuant to this paragraph shall not be considered final for judicial review.”
Further, § 41.50(b) also provides that Appellants, WITHIN TWO MONTHS
FROM THE DATE OF THE DECISION, must exercise one of the
following two options with respect to the new grounds of rejection to avoid
termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate amendment of the
claims so rejected or new evidence relating to the claims so rejected, or both,
and have the matter reconsidered by the examiner, in which event the
prosecution will be remanded to the examiner. . . .
(2) Request rehearing. Request that the proceeding be reheard
under § 41.52 by the Board upon the same record. . . .
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED-IN-PART
37 C.F.R. § 41.50(b)