Jian Li et al.

Patent Trials and Appeals Board

Aug 6, 2019

14242485 - (D) (P.T.A.B. Aug. 6, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/242,485 04/01/2014 Jian Li 10829-9110.US00 9886
46844 7590 08/06/2019
PERKINS COIE LLP - Micron
PATENT-SEA
PO BOX 1247
SEATTLE, WA 98111-1247
EXAMINER
KIELIN, ERIK J
ART UNIT PAPER NUMBER
2814
NOTIFICATION DATE DELIVERY MODE
08/06/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patentprocurement@perkinscoie.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte JIAN LI and STEVEN K. GROOTHUIS
____________

Appeal 2018-006666
Application 14/242,4851
Technology Center 2800
____________
Before DONNA M. PRAISS, DEBRA L. DENNETT, and
SHELDON M. MCGEE, Administrative Patent Judges.
MCGEE, Administrative Patent Judge.
DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134, Appellant seeks our review of the
Examiner’s rejection of claims 1, 3, 4, 6–8, 16–18, 20, and 35–48. App. Br.
8–9.
We have jurisdiction. 35 U.S.C. § 6.
We affirm.

1 Appellant is the Applicant, Micron Technology, Inc., which is also
identified as the real party in interest. App. Br. 3.
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Application 14/242,485
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BACKGROUND
The subject matter on appeal as set forth in independent claims 1 and
16 is directed to semiconductor die assemblies having, inter alia, multiple
logic dies positioned in the same stack with a plurality of memory dies
positioned between a first and second logic die. App. Br. 26–27, 29.
Claim 1 is illustrative of the appealed subject matter, and is copied
below from the Claims Appendix to the Appeal Brief.
1. A semiconductor die assembly, comprising:
a package substrate;
a first logic die including first bond pads and a memory
controller operably coupled to the first bond pads;
a second logic die positioned on the package substrate and
including second bond pads, a communication component
operably coupled to the second bond pads, and a peripheral
portion extending beyond a footprint of the first logic die,
wherein the communication component is configured to
deserialize serial data received over the package substrate into
parallel data streams;
a stack of memory dies positioned on the second logic die
and disposed between the first and second logic dies, wherein the
first logic die is positioned on the stack of memory dies;
a plurality of through-stack interconnects collectively
forming a parallel data connection between the memory
controller and the communication component, wherein each of
the through-stack interconnects extends through the entire stack
of memory dies to connect one of the first bond pads of the first
logic die to a corresponding one of the second bond pads of the
second logic die for receiving one of the parallel data streams,
and wherein the through-stack interconnects are arranged to
provide the parallel data streams to the memory controller
simultaneously over the parallel data connection;
a thermally conductive casing having a cap portion over
the first logic die and a wall portion extending from the cap
portion, wherein the wall portion has a bottom surface attached
to only the second logic die at the peripheral region and is
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configured to dissipate heat produced by the communication
component during operation; and
a dielectric underfill material at least partially
encapsulating at least one of the first logic die, second logic die,
and memory dies, wherein the dielectric underfill material
contacts the thermally conductive casing.
Id. at 26–27.

The Examiner rejects claims 1, 3, 4, 6–8, 16–18, 20, and 35–48 under
35 U.S.C. § 103(a) as set forth on pages 3–32 of the Final Office Action
dated July 17, 2017.
OPINION
Appellant argues limitations present in independent claim 1, but does
not advance separate arguments directed to any other claim. App. Br. 14–
24. We, therefore, select claim 1 as representative and decide the appeal on
the basis of claim 1 alone. See 37 C.F.R. § 41.37(c)(1)(iv).
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of the arguments and evidence produced
thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential),
cited with approval in In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011)
(“[I]t has long been the Board’s practice to require an applicant to identify
the alleged error in the examiner’s rejections.”).
The dispositive issue in this appeal is whether Appellant has identified
reversible error in the Examiner’s determination that, based on the collective
teachings of the prior art, it would have been obvious to separate the
memory controller and the communication component onto two separate
logic dies located in the same stack as recited in claim 1.
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We have considered Appellant’s arguments (App. Br. 8–24; Reply Br.
1–5) and are unpersuaded that Appellant has identified any such error.
Therefore, we sustain the obviousness rejections of claim 1––and thus all
claims on appeal––based on the findings of fact, conclusions of law, and
rebuttals to arguments well-expressed by the Examiner in the Final Action
and in the Answer. We add the following only for emphasis.
In arguing that the cited references fail to disclose or suggest each
element of claim 1, Appellant addresses the teachings of the Hung2 and Wu3
references separately. App. Br. 14–15. Consistent with the oft-stated
principle set forth by our reviewing court, such arguments are unpersuasive
because “[n]on-obviousness cannot be established by attacking references
individually where the rejection is based upon the teachings of a
combination of references. . . . [The reference] must be read, not in
isolation, but for what it fairly teaches in combination with the prior art as a
whole.” In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
We furthermore discern no persuasive merit in Appellant’s argument
that the Examiner’s “proposed combination of Hung and Wu would render
Hung unsatisfactory for its intended purpose and change its principle of
operation.” App. Br. 16–18. Here, we express our agreement with the
Examiner (Ans. 35–37) that Appellant argues the bodily incorporation of
Wu’s features into Hung’s structure, and has furthermore failed to provide
evidence establishing that “additional circuitry” would be required to
accomplish the Examiner’s proffered modification of Hung to separate

2 US 2015/0035135 A1, published Feb. 5, 2015.
3 US 8,546,955 B1, issued Oct. 1, 2013.
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controller functionality and SERDES functionality onto separate dies. App.
Br. 17. Without evidentiary support that additional circuitry would be
required, and that such circuitry would, in fact, change Hung’s principle of
operation, the preponderance of the evidence supports the Examiner’s
determination that Hung and Wu are properly combinable.
Finally, we stress our disagreement with Appellant’s argument that
the Examiner provided an insufficient rationale regarding why the skilled
artisan would have been motivated to combine the teachings of Hung and
Wu. App. Br. 19–21. Here, the Examiner provides numerous reasons why
the skilled artisan would have been so motivated (Final Act. 9–11), some of
which are not addressed by Appellant. For example, Appellant does not
specifically respond to the Examiner’s determinations that separating the
memory and controller functions onto separate dies would have been a finite
number of predictable solutions with a reasonable expectation of success
and, furthermore, would have been an obvious arrangement of parts. Id. at
11.
For these reasons, and those provided by the Examiner, we hold that
Appellant has failed to identify reversible error in the Examiner’s rejections
of claims 1, 3, 4, 6–8, 16–18, 20, and 35–48. We, therefore, sustain the
Examiner’s rejections of these claims.

DECISION
The Examiner’s final decision to reject claims 1, 3, 4, 6–8, 16–18, 20,
and 35–48 is affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

Appeal 2018-006666
Application 14/242,485
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AFFIRMED