Jeffrey W. Waldrip et al.

Patent Trials and Appeals Board

Jun 26, 2020

2018005455 (P.T.A.B. Jun. 26, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/152,462 05/11/2016 Jeffrey W. Waldrip 01.P53797C 8001
119829 7590 06/26/2020
Green, Howard, & Mughal LLP
5 Centerpointe Dr.
Suite 400
Lake Oswego, OR 97035
EXAMINER
GANNON, LEVI
ART UNIT PAPER NUMBER
2849
NOTIFICATION DATE DELIVERY MODE
06/26/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@ghmip.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte JEFFREY W. WALDRIP, YONGPING FAN, and JING LI
____________________

Appeal 2018-005455
Application 15/152,462
Technology Center 2800
____________________

Before MICHAEL P. COLAIANNI, DONNA M. PRAISS, and
N. WHITNEY WILSON, Administrative Patent Judges.

WILSON, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
September 25, 2017 decision finally rejecting claims 13, 15–20, and 22–26
(“Final Act.”). We have jurisdiction over the appeal under 35 U.S.C. § 6(b).
We affirm.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies Intel Corporation as the real party in
interest (Appeal Br. 1).
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Application 15/152,462

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CLAIMED SUBJECT MATTER
Appellant’s disclosure generally relates to phase locked loop (PLL)
circuits, and in particular, to a circuit for calibrating an inductor capacitor
PLL (LCPLL) (Spec. ¶¶ 2, 3). Such LCPLL’s are said to be useful for
generating accurate clocks for transmitting and receiving data (Spec. ¶ 3).
LCPLL’s are said to use automatic frequency control (AFC) techniques to
calibrate oscillator settings to conform about an operable control voltage
range (id.). The disclosure describes what is said to be an improved system
for setting these frequencies which handles variations incurred by differing
temperatures (Spec. ¶¶6, 7). Details of the claimed apparatus are set forth in
representative claim 13, which is reproduced below from the Claims
Appendix to the Appeal Brief:
13. An apparatus comprising:
a digitally controlled oscillator (DCO) including
capacitors that can be enabled or disabled to change a
capacitance loading to change an oscillating frequency of the
DCO;
a first control having a first code to adjust the capacitance
loading of the DCO by a coarse amount such that a phase
locked loop (PLL) is locked for a target clock frequency;
a second control having a second code to adjust the
capacitance loading of the DCO by a fine amount, wherein the
fine amount is to change the capacitance loading by a smaller
amount than a change in the capacitance loading by the coarse
amount, and wherein the first control is applied prior to the
application of the second control; and
an automatic frequency control (AFC) circuitry to
provide the first and second controls such that the second code
has a value which is near a middle of a range of values of the
second code when a temperature is to be at a mid-range value[;]
wherein the AFC circuitry comprises:
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a calibration logic, coupled to the DCO, to
generate the first control to lock the PLL prior to
adjusting of the capacitance loading of the DCO by the
fine amount by the second control, wherein the PLL
includes the DCO;
a multiplexer coupled to the DCO; and
a circuitry coupled to a first input of the
multiplexer, wherein the circuitry is to generate the
second control during a calibration mode, wherein the
multiplexer has a second input to receive an output of a
digital low pass filter (DLPF).

REJECTIONS
1. Claims 13, 15–20, and 22–26 are rejected under
35 U.S.C. § 103(a) as unpatentable over Costa2 in view of Sakurai.3
2. Claims 13, 15–20, and 22–26 are rejected under
35 U.S.C. § 103(a)4 as unpatentable over Liu5 in view of Sakurai.

DISCUSSION
Appellant argues independent claims 13 and 18 together (see, e.g.,
Appeal Br. 8–11), but makes separate arguments for the two rejections, and
makes a separate argument regarding claims 19 and 20 (as a pair) and claim

2 Costa et al, US 7,463,097 B2, issued December 9, 2008.
3 Sakurai et al., US 2009/0302958 A1, published December 10, 2009.
4 The Final Action indicates in the statement of the rejection that the
rejection was under §102(e) (Final Act. 10). However, Appellant and the
Examiner acknowledge understanding that this was an error and that the
rejection was intended to be made under §103(a) (Appeal Br. 6; Ans. 2).
5 Liu et al, US 8,253,506 B2, issued August 28, 2012.
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17 (see, Appeal Br. 11–13). The remaining dependent claims (claims 24–
26) are not argued separately from claims 13 and 18.
Claims 13 and 18 over Costa in view of Sakurai. The Examiner’s
findings regarding the rejection of claim 13 over Costa in view of Sakurai
are found at pages 3 and 4 of the Final Action. The Examiner finds that
Costa discloses each of the elements of claim 13, except that Costa does not
disclose a second control comprising a second code (Final Act. 4). The
Examiner further finds that Sakurai teaches controlling fine tuning
capacitors in an LC oscillator with digital control codes (Final Act. 4, citing
Sakurai ¶ 39). The Examiner also finds that Sakurai teaches a capacitor
bank structure used for finely, digitally tuned capacitors (id.). The Examiner
determines that it would have been obvious to replace the analog fine control
signals of Costa with digital fine control codes as taught by Sakurai
“because such a modification would have been merely a replacement of well
known, art recognized functionally equivalent fine tuning capacitor control
signals that would yield predictable results in the oscillator of Costa” (id.)
Appellant makes several arguments urging reversal of this rejection.
First, Appellant contends that the Examiner improperly relied on hindsight
in making the combination, because nothing in Costa suggests using a digital
code for the second control to adjust capacitance by a fine amount, and
because there is no benefit to Costa in using a digital code (Appeal Br. 8–9).
This argument is not persuasive because, as explained by the Examiner, the
proposed combination is simply the “substitution of one known element for
another” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007). In this
instance, it is the substitution of a digital code, which was known – as shown
by Sakurai – for an analog controller as used by Costa. The Examiner finds
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that making this substitution would yield predictable results in Costa’s
oscillator (Final Act. 4). Therefore, a person of skill in the art would have
found making this substitution to have been obvious. KSR, 550 U.S. at 417.
Appellant contends that the proposed combination would not have
been a simple substitution because it would have required “changing the
entire architecture of Costa which is designed around analog circuitry”
(Appeal Br. 9). However, as explained by the Examiner (Ans. 3), the use of
digital oscillator tuning codes instead of analog tuning codes is a basic
modification that was well-known and well-established, and well within the
ability of one of ordinary skill in the art. Appellant does not challenge this
finding, arguing only that one of skill in the art would not have made the
substitution because Costa calls for the use of an analog system.
Second, Appellant argues that Costa does not disclose a second
control having a second code. The Examiner finds that Costa’s Vtune
corresponds to the second control (Final Act. 3). Appellant argues that
Costa’s Vtune node receives “an analog voltage and not a code” (Appeal Br.
10). This argument is not persuasive, because the Examiner acknowledges
that Costa does not teach the use of a second digital code, and there is no
dispute that there is a difference between an analog signal and a digital
signal. However, the use of a second digital code, as taught by Sakurai (and
other references noted by the Examiner) remedies this deficiency in Costa.
Third, Appellant argues that Costa does not teach or suggest the
limitation “an automatic frequency control (AFC) circuitry to provide the
first and second controls such that the second code has a value which is near
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a middle of a range of values of the second code when a temperature is to be
at a mid-range value” (Appeal Br. 14). Appellant contends that:
The alleged Fig. 6 of Costa only shows “an example of simulated
Vtune_cal vs temperature curves (A-C) that can be generated by the
embodiment of the temperature variable voltage source 30.” That alone
provides no disclosure that the second control is to have an associated
code which is near a middle of a range of the associated code when a
temperature is to be at a mid-range value. Again, Examiner is
respectfully requested to consider all words of the claim.
(Appeal Br. 14). This argument is not persuasive. In the rejection, the
voltage Vtune_cal corresponds to the claimed code, with the Examiner
demonstrating that a middle range voltage corresponds to the mid-range
temperature value. As detailed by the Examiner, Costa admittedly does not
disclose a digital second code, but this is suggested by the combined
teachings of Costa and Sakurai.
Claims 13 and 18 over Liu and Sakurai. The Examiner’s findings
with respect to the rejection over Liu and Sakurai parallel the findings with
respect to Costa and Sakurai, in that the Examiner finds that Liu teaches
each of the claimed limitations except the second control comprising a
second code (Final Act. 10–11).
Appellant contends that Liu teaches that V1(T) is a voltage that varies
with temperature, but is not shown to adjust the capacitance by a fine
amount (Appeal Br. 13–14). Appellant alleges that V1(T) is a bias voltage
that changes the reference to one of the capacitor nodes, but does not adjust
its capacitance (Appeal Br. 14). The Examiner cites col. 7, lines 49–51 of
Liu – which discloses that “Multiplexing circuit 90 couples a selected one of
fine tuning analog signal VTUNE and temperature compensation analog
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signal V1(T) onto control node N5” – as teaching the limitation that the
second code adjusts the capacitance loading of the DCO by a fine amount.
Appellant’s argument is persuasive, as we agree that the Examiner has not
adequately explained how the cited passage from Liu shows an adjustment
of the capacitance loading.
The Examiner has the initial burden of establishing a prima facie case
of obviousness based on an inherent or explicit disclosure of the claimed
subject matter under 35 U.S.C. § 103. In re Oetiker, 977 F.2d 1443, 1445
(Fed. Cir. 1992) (“[T]he examiner bears the initial burden, on review of the
prior art or on any other ground, of presenting a prima facie case of
unpatentability.”). To establish a prima facie case of obviousness, the
Examiner must show that each and every limitation of the claim is described
or suggested by the prior art or would have been obvious based on the
knowledge of those of ordinary skill in the art. In re Fine, 837 F.2d 1071,
1074 (Fed. Cir. 1988). In this instance, we determine that Appellant has
demonstrated that the preponderance of the evidence of record does not
support the Examiner’s finding that Liu teaches a second control to adjust a
capacitance loading of a DCO by a fine amount. Accordingly, we reverse
the rejection over Liu in view of Sakurai.
Claims 17, 19, and 20. Appellant contends that the Examiner failed
to provide sufficient evidence to support the factual findings supporting the
rejections of these claims (Appeal Br. 11–12). In particular, Appellant
challenges the Examiner’s finding in connection with claims 19 and 20 that
“it is well-known to those of ordinary skill in the art to use a transmitter with
serial IO PCle technology” (Final Act. 8), and in connection with claim 17
that it was well known “to generate a control voltage for a DCO from a
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reference clock and an output of the DCO” (Final Act. 6). Appellant
contended that the Examiner was required to provide adequate evidence to
support these findings (Appeal Br. 11–12). The Examiner supplied the
requested evidence in the Answer (see Ans. 4–5), and Appellant does not
argue that this evidence is insufficient. Accordingly, we determine that this
argument does not show reversible error in the rejections.

CONCLUSION

In summary:

Claims
Rejected
35 U.S.C.
§
Basis Affirmed Reversed
13, 15–20,
22–26
103(a) Costa, Sakurai 13, 15–20,
22–26

13, 15–20,
22–26
103(a) Liu, Sakurai 13, 15–20,
22–26
Overall
Outcome
13, 15–20,
22–26

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED