JANUS TECHNOLOGIES, INC.

Patent Trials and Appeals Board

Dec 14, 2020

2019005325 (P.T.A.B. Dec. 14, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/971,604 08/20/2013 Sofin RASKIN 111491-0105 (JTI-009) 6532
38706 7590 12/14/2020
FOLEY & LARDNER LLP
3000 K STREET N.W.
SUITE 600
WASHINGTON, DC 20007-5109
EXAMINER
LIN, AMIE CHINYU
ART UNIT PAPER NUMBER
2436
NOTIFICATION DATE DELIVERY MODE
12/14/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ipdocketing@foley.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte SOFIN RASKIN, JOSHUA PORTEN,
MICHAEL WANG, and KUEN YU LAI
____________________

Appeal 2019-005325
Application 13/971,604
Technology Center 2400
____________________

Before ALLEN R. MacDONALD, CAROLYN D. THOMAS and
MICHAEL J. STRAUSS, Administrative Patent Judges.

MacDONALD, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–28. Appeal Br. 2. We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 Appellant identifies the real party in interest is Janus Technologies, Inc.
Appeal Br. 2.
Appeal 2019-005325
Application 13/971,604

2
CLAIMED SUBJECT MATTER
Claim 1 is illustrative of the claimed subject matter (emphasis,
formatting, and bracketed material added):
1. A computer system, comprising:
[A.] a network interface for sending and receiving data over
a network;
[B.] a host computer processor that executes an operating
system and applications that generate and utilize the
data sent and received over the network; and
[C.] a secure subsystem interposed between the host
computer processor and the network interface for
capturing certain of the data sent and received via the
network interface, wherein the secure subsystem
includes:
[i.] snoop logic that selects for capturing into a buffer a
local copy of only the certain data,
[a.] the local copy being a duplicate subset of the
data that is also sent and received over the
network and less than all of the data sent and
received over the network via the network
interface,
[b.] wherein a ratio between the local copy of the
data that has been captured into the buffer
based on the selecting and all of the data that is
sent and received via the network interface is
controlled by the snoop logic in accordance
with at least a bandwidth of the network
interface, and
[ii.] a controller that configures how the snoop logic
selects for capturing only the certain data.

Appeal 2019-005325
Application 13/971,604

3
REFERENCES2
The Examiner relies on the following references:
Name Reference Date
Wiederin US 2004/0268147 A1 Dec. 30, 2004
O’Toole, Jr. US 7,467,408 B1 Dec. 16, 2008
Chan US 7,636,653 B1 Dec. 22, 2009
Khan US 2010/0214926 A1 Aug. 26, 2010
Choi US 2013/0160122 A1 June 20, 2013
Ahuja US 2013/0254838 A1 Sept. 26, 2013
Pope US 2014/0355613 A1 Dec. 4, 2014
This Panel cites the following additional references:
Name Reference Date
Sprinkle US 2010/0262766 A1 Oct. 14, 2010
Borchers US 2010/0262979 A1 Oct. 14, 2010
REJECTIONS3
A.
The Examiner rejects claims 1, 3–12, 14–16, 18–21, 25, and 26, under
35 U.S.C. § 103(a) as being unpatentable over the combination of Pope,
O’Toole, Jr., and Khan. Final Act. 5–13.
We select claim 1 as the representative claim for this rejection.
Except for our ultimate decision, we do not address the merits of the
§ 103(a) rejection of claims 3–12, 14–16, 18–21, 25, and 26 further herein.

2 All citations herein to patent and pre-grant publication references are by
reference to the first named inventor only.
3 The Examiner indicates that a rejection of claims 1–28 under 35 U.S.C.
§ 112(a) as failing to comply with the written description requirement (Final
Act. 3–4) has been overcome (Oct. 17, 2018 Advisory Act. 1).
Appeal 2019-005325
Application 13/971,604

4
B.
The Examiner rejects claims 2, 13, 17, 22–24, 27, and 28, under
35 U.S.C. § 103 as being unpatentable over Pope, O’Toole, Jr., and Khan in
various combinations with Wiederin, Chan, Choi, and Ahuja. Final Act. 13–
18.
We do not find separate arguments directed to the rejections of
these claims. Thus, the rejections of these claims turn on our decision as
to claim 1. Except for our ultimate decision, we do not address the merits
of the § 103(a) rejections of these claims further herein.
OPINION
We have reviewed the Examiner’s rejections in light of Appellant’s
Appeal Brief and Reply Brief arguments.
A.1.
Appellant raises the following argument in contending that the
Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a).
The Office Action relies on Pope for disclosing the
claimed controller that configures the snoop logic. However, this
reliance is misplaced. Pope discloses a packet capture unit 114
and a controller 113. The packet capture unit 114 is described as
identifying packet flows for duplication and capturing using “a
set of one or more triggers” in para. [0086]. However, nowhere
does Pope teach or suggest how these “triggers” are configured,
much less by controller 113. Cited paragraph [0089] merely
discloses that packet capture unit 114 is implemented by a
reconfigurable logic device such as a FPGA. This merely
describes one possible way that the unit 114 is physically
implemented, not how it is configured by a separate controller
for selecting how to capture data, as would be required to meet
the explicit limitations of the claims.
Appeal 2019-005325
Application 13/971,604

5
The Advisory Action takes the position that:
Examiner respectfully disagrees. It should be
noted that claim 1 only recites “a controller that
configures how the snoop logic selects for capturing
only the certain data”, the claim does NOT specify
how the snoop logic is configured by the controller,
in other words, how the snoop logic is configured
by the controller is NOT required by the claim, in
addition, the claim only recites “a controller” but
does NOT further specify on the structure of the
controller, and the claim does NOT require a
separate controller as argued by Applicant. To
further clarify, Pope teaches select for capturing
specific data, and P[o]pe teaches “a controller”
which has been broadly interpreted as, for
example, the one or more firmware modules that
control the reconfigurable logic device (see e.g.
[0086]-[0087], [0089]). Thus, Pope teaches “a
controller that configures how the snoop logic
selects for capturing only the certain data” as recited
in claim 1.
This position totally ignores the requirements of the claims
as a whole, which further limit the claimed controller to a
component in the claimed secure subsystem that is interposed
between a host processor and a network interface. As such, it is
improper to “broadly” construe the claimed controller as “one
or more firmware modules” as the Advisory Action does.
Appeal Br. 6–7 (panel emphasis added).
A.2.
The Examiner responds:
[C]ited prior art Pope teaches the packet capture unit 114
interposed between (logically or physically intervened/placed
between) the host data processing device 101 and the network
interface 201. . . . In other words, the packet capture unit 114
has been interpreted as the “secure subsystem” recited in the
claims, the host data processing device 101 has been interpreted
Appeal 2019-005325
Application 13/971,604

6
as the “host computer processor” recited in the claims, and the
network interface 201 has been interpreted as the “network
interface” recited in the claims.
Pope also teaches the packet capture unit 114 is a
reconfigurable logic device having one or more firmware
modules, that is, the one or more firmware modules are installed
at the packet capture unit 114 which is interposed between the
host data processing device 101 and the network interface 201
(see e.g. [0031], “ . . . the packet capture unit is a reconfigurable
logic device such as an FPGA. . . the packet inspector,
duplication engine and packet capture engine are defined by one
or more firmware modules installed at the reconfigurable logic
device . . . “ [0089], “ . . . Packet capture unit 114 is preferably a
reconfigurable logic device, such as an FPGA, with packet
inspector 203, duplication engine 204 and packet capture
engine 205 being functional components defined at the
reconfigurable logic device by one or more firmware modules .
. . . “).
In addition, it should be noted that the claims do not
require the claimed controller to be separated from the claimed
snoop logic, in other words, the controller can overlap with the
snoop logic. Moreover, the controller can overlap with the
claimed secure subsystem. Since the specification and the claims
do not provide any special definition for the term “controller”
and the claims do not specify the structure of the “controller”,
under the broadest reasonable interpretation, this term has
been interpreted as any software, hardware, or combination of
software and hardware that controls. In this case, the one or
more firmware modules installed at the packet capture unit 114
is just an example of the components disclosed in Pope that can
be interpreted as the controller, the controller can be interpreted
as other elements disclosed in Pope such as the processor of the
packet capture unit 114/reconfigurable logic device/FPGA.
Examiner also notes that the specification and the claims do not
provide any special definition for the term “configures”, thus
under the broadest reasonable interpretation, the term
“configures” has been interpreted as any type of controlling,
arranging, setting up, defining or designing. Furthermore, note
Appeal 2019-005325
Application 13/971,604

7
that firmware by definition refers to embedded software that
controls how computer components function.
Ans. 4–5 (panel emphasis added).
A.3.
Appellant further argues:
This position is clearly erroneous because it does not
respect the invention as a whole as set forth in the claims. To
support a rejection under Section 103, all claim limitations must
be considered. And the claims clearly define separate elements
of [l] snoop logic that selects for capturing into a buffer a local
copy of only the certain data, and [2] a controller that configures
how the snoop logic selects for capturing only the certain data.
At its core, the Examiner’s position is that packet capture
unit 114 contains a bunch of “overlapping” modules some of
which may be considered performing functions of the claimed
“snoop logic” in connection with some limitations, and functions
of the claimed “controller” in connection with other limitations,
because the claims are not specific enough. This position is
improper. The Examiner must consistently identify an element
within packet capture unit 114 that performs the limitations of
the claimed snoop logic of selecting for capturing into a buffer a
local copy of only the certain data. Likewise, the Examiner must
consistently identify a separate element within packet capture
unit 114 that performs the limitations of the claimed controller
of configuring how the snoop logic selects for capturing only the
certain data. The Examiner’s inability to do so is not a fault of
the claims as set forth in the Examiner’s Answer. Rather, it is the
fault of the prior art cited not teaching or suggesting all claim
limitations.
Reply Br. 4 (panel emphasis added).
B.
We are unpersuaded by Appellant’s argument. First, Appellant
characterizes Examiner’s position as one of “a bunch of ‘overlapping’
modules some of which may be considered performing functions of the
Appeal 2019-005325
Application 13/971,604

8
claimed ‘snoop logic’ in connection with some limitations, and functions of
the claimed ‘controller’ in connection with other limitations,” as opposed to
the “separate elements” required by claim 1. Id. We disagree with
Appellant’s characterization. Rather, the Examiner points to (a) Pope’s
packet capture unit 114 as the secure subsystem (Ans. 4), (b) Pope’s packet
inspector 203, duplication engine 204 and packet capture engine 205 as the
functional components (i.e., snoop logic) (Ans. 5), and Pope’s firmware as
the controller that configures the snoop logic (Advisory Act. 2).
Second, contrary to Appellant’s argument that it is improper to
construe Pope’s firmware as the required controller that configures, we agree
with the Examiner’s reasoning. Appellant points out that the claimed
controller “can be implemented as a CPU running embedded software” or
“can be implemented entirely in hardware.” Spec. ¶ 41. We agree with the
Examiner’s reasoning because firmware is a long-standing art recognized
equivalent for Appellant’s software and hardware configuring examples.
firmware Software routines stored in read-only memory
(ROM). Unlike random access memory (RAM), read-only
memory stays intact even in the absence of electrical power.
Startup routines and low-level input/output instructions are
stored in firmware. It falls between software and hardware in
ease of modification.
Microsoft Press Computer Dictionary 1991.
Also, although not required for our decision, we provide a further
example that discloses in more detail configuring a FPGA using firmware as
in Pope.
In another exemplary implementation, the controller 110 is a
FPGA controller. The FPGA controller may be implemented in
hardware, software, or a combination of hardware and software.
For example, the FPGA controller may be loaded with firmware
Appeal 2019-005325
Application 13/971,604

9
from memory (e.g., memory module 116) including instructions
that, when executed, may cause the FPGA controller to perform
in a certain manner. . . . For instance, the memory module 116
may be configured to store one or more images for the FPGA
controller, where the images include firmware for use by the
FPGA controller.
Borchers ¶ 114–116 and figure 1A; see also Sprinkle ¶ 30–31.
CONCLUSION
The Examiner has not erred in rejecting claims 1–28 as being
unpatentable under 35 U.S.C. § 103(a).
The Examiner’s rejections of claims 1–28 as being unpatentable under
35 U.S.C. § 103(a) are affirmed.
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1, 3–12,
14–16, 18–
21, 25, 26
103(a) Pope, O’Toole, Jr.,
Khan,
1, 3–12, 14–
16, 18–21,
25, 26

2, 13, 17,
22, 23
103(a) Pope, O’Toole, Jr.,
Khan, Wiederin
2, 13, 17,
22, 23

24 103(a) Pope, O’Toole, Jr.,
Khan, Wiederin, Ahuja
24
27 103(a) Pope, O’Toole, Jr.,
Khan, Chan
27
28 103(a) Pope, O’Toole, Jr.,
Khan, Choi
28
Overall
Outcome

1–28

Appeal 2019-005325
Application 13/971,604

10
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED