International Business Machines Corporation

Patent Trials and Appeals Board

May 28, 2020

14573273 - (D) (P.T.A.B. May. 28, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/573,273 12/17/2014 Son T. Dao DE920140036US2 6747
11432 7590 05/28/2020
IBM Corporation - Endicott Drafting Center
11501 Burnet Road
Austin, TX 78758
EXAMINER
LAROCQUE, EMILY E
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
05/28/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
edciplaw@us.ibm.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte SON T. DAO and SILVIA MELITTA MUELLER

Appeal 2019-001980
Application 14/573,273
Technology Center 2100
____________

Before DEBRA K. STEPHENS, MICHAEL M. BARRY, and
PHILLIP A. BENNETT, Administrative Patent Judges.

BARRY, Administrative Patent Judge.

DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 30–38, which are all of the pending
claims. See Appeal Br. 11–19; Final Act. 1, 4–17. We have jurisdiction
under 35 U.S.C. § 6(b).
We REVERSE.

1 We use “Appellant” to refer to the “applicant” as defined in 37 C.F.R.
§ 1.42. Appellant identifies International Business Machines Corporation as
the real party in interest. Appeal Br. 3.
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Introduction
The Specification states the “invention relates generally to the field of
floating point processing, and more particularly to determining overflow/
underflow conditions.” Spec. ¶ 1. Discussing the background of the
invention, the Specification explains:
Floating point numbers may be used to represent a large
range of numbers using a limited number of bits. Floating point
numbers act as if there is no fixed number of bits before or after
the decimal point; that is, the decimal point can float. Floating
point numbers are represented by a number value[2] and an
exponent associated with that number value. Due to the added
complexity of handling both a value and an exponent when
performing calculations with floating point numbers, some
processors comprise floating point processors. Floating point
processors are specialized processors designed for performing
floating point arithmetic, such as addition, subtraction,
multiplication, division, bit shifting and other operations.
While floating point numbers typically have larger ranges than
integer number[s], the representations of floating point numbers
still have limits based on the amount of storage used to store the
representation. The limits of a floating point numbers
representation are based primarily of the range of exponents
that can be stored. When the exponent falls outside this range
underflow or overflow occurs.
Id. ¶ 2.
Claim 30 is illustrative of the claims on appeal:
30. A method comprising:
receiving, by a set of processor(s), an intermediate result
for an addition operation, with the intermediate result including
an intermediate significand and an intermediate exponent;
determining, by the processor(s) set, a mask based, at
least in part, on the value of the intermediate exponent;

2 The number value maps to the “significand” in the claims.
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applying, by the processor(s) set, the mask to the
intermediate significand to obtain a masked significand; and
generating, by the processor(s), an overflow condition
code based, at least in part, a value of the masked significand.
Appeal Br. 17 (Claims App’x).
The Rejections
The Examiner rejected claims 30–38 under 35 U.S.C. § 101 as
directed to a judicial exception (i.e., an abstract idea) without reciting
significantly more. Final Act. 4–7.
The Examiner rejected claims 30–32 and 36–38 under 35 U.S.C.
§ 103 as obvious over Rubanovich (US 2014/0379773 A1; Dec. 25, 2014),
Gschwind (US 2013/0212139 A1; Aug. 15, 2013), and Huck (US 6,151,669;
Nov. 21, 2000). Final Act. 8–12.
The Examiner rejected claims 33–35 under § 103 as obvious over
Rubanovich, Gschwind, Huck, and Putrino (US 5,805,475; Sept. 8, 1998).
Final Act. 12–16.
The § 101 Rejection
§ 101 Law and the USPTO 2019 Guidance
An invention is patent-eligible if it claims a “new and useful process,
machine, manufacture, or composition of matter.” 35 U.S.C. § 101. The
Supreme Court, however, has long interpreted 35 U.S.C. § 101 to include
implicit exceptions: “[l]aws of nature, natural phenomena, and abstract
ideas” are not patentable. E.g., Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 573
U.S. 208, 216 (2014).
In determining whether a claim falls within an excluded category, we
are guided by the Supreme Court’s two-step framework, described in Mayo
and Alice. Id. at 217–18 (citing Mayo Collaborative Servs. v. Prometheus
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Labs., Inc., 566 U.S. 66, 71–73 (2012)). In accordance with that framework,
we first determine what concept the claim is “directed to.” See Alice, 573
U.S. at 219 (“On their face, the claims before us are drawn to the concept of
intermediated settlement, i.e., the use of a third party to mitigate settlement
risk.”); see also Bilski v. Kappos, 561 U.S. 593, 611 (2010) (“Claims 1 and 4
in petitioners’ application explain the basic concept of hedging, or protecting
against risk.”).
Concepts determined to be abstract ideas, and, thus, patent ineligible,
include certain methods of organizing human activity, such as fundamental
economic practices (Alice, 573 U.S. at 219–20; Bilski, 561 U.S. at 611);
mathematical concepts (Parker v. Flook, 437 U.S. 584, 594–95 (1978)); and
mental processes (Gottschalk v. Benson, 409 U.S. 63, 67 (1972)). In
Diamond v. Diehr, the claim at issue recited a judicial exception in the
category of mathematical concepts, but the Supreme Court held that “[a]
claim drawn to subject matter otherwise statutory does not become
nonstatutory simply because it uses a mathematical formula.” 450 U.S. 175,
176 (1981).
If the claim is “directed to” an abstract idea, we turn to the second
step of the Alice and Mayo framework, where “we must examine the
elements of the claim to determine whether it contains an ‘inventive
concept’ sufficient to ‘transform’ the claimed abstract idea into a patent-
eligible application.” Alice, 573 U.S. at 221 (internal citation omitted). “A
claim that recites an abstract idea must include ‘additional features’ to
ensure ‘that the [claim] is more than a drafting effort designed to
monopolize the [abstract idea].’” Id. (quoting Mayo, 566 U.S. at 77).
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“[M]erely requiring generic computer implementation fails to transform that
abstract idea into a patent-eligible invention.” Id. at 212.
In 2019, the USPTO published revised guidance on the application of
§ 101. 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed.
Reg. 50–57 (“2019 Guidance”); see also October 2019 Update: Subject
Matter Eligibility, 84 Fed. Reg. 55942–53 (“2019 Guidance Update”)
(available at www.uspto.gov/sites/default/files/documents/peg_oct_2019_
update.pdf) (providing “examples as well as a discussion of various issues
raised by the public comments” to the 2019 Guidance). Under the 2019
Guidance, we first look to whether the claim recites:
(1) any judicial exceptions, including certain groupings
of abstract ideas (i.e., mathematical concepts, certain methods
of organizing human activity such as a fundamental economic
practice, or mental processes); and
(2) additional elements that integrate the judicial
exception into a practical application (see Manual of Patent
Examining Procedure (MPEP) § 2106.05(a)–(c), (e)–(h)).3
See 84 Fed. Reg. at 52, 54–55. Only if a claim (1) recites a judicial
exception and (2) does not integrate that exception into a practical
application, do we then look to whether the claim:
(3) adds a specific limitation beyond the judicial
exception that are not “well-understood, routine, conventional”
in the field (see MPEP § 2106.05(d)); or
(4) simply appends well-understood, routine,
conventional activities previously known to the industry,
specified at a high level of generality, to the judicial exception.
See 2019 Guidance, 84 Fed. Reg. at 56.

3 All references to the MPEP are to the 9th Ed., Rev. 08.2017 (Jan. 2018).
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Our § 101 Analysis
Appellant argues error in the § 101 rejection based solely on the
independent claims. See Appeal Br. 12–13. We select claim 30 as
representative for this rejection. 37 C.F.R. § 41.37(c)(1)(iv) (2017).
Alice/Mayo Step One, Revised Guidance Step 2A Prong One
At prong one, we put aside that each step requires performing all
recited functionality by the same “set of processor(s),” and consider the
following limitations:
[a] receiving . . . an intermediate result for an addition
operation, with the intermediate result including an intermediate
significand and an intermediate exponent;
[b] determining . . . a mask based, at least in part, on the
value of the intermediate exponent;
[c] applying . . . the mask to the intermediate significand
to obtain a masked significand; and
[d] generating . . . an overflow condition code based, at
least in part, a value of the masked significand.
Step (a) describes (recites) receiving a floating point number that is an
“intermediate result for an addition operation.” This implicitly requires that,
prior to performing this step, a process of adding has previously commenced
but not yet completed (i.e., the adding process is ongoing). Obtaining an
intermediate value from an ongoing process of adding numbers, as recited, is
abstract in the category of mathematical concepts. 2019 Guidance, 84 Fed.
Reg. at 52; cf., e.g., SAP Am., Inc. v. InvestPic, LLC, 898 F.3d 1161, 1164–
65, 1168 (Fed. Cir. 2018) and Digitech Image Techs., LLC v. Elecs. for
Imaging, Inc., 758 F.3d 1344, 1350–51 (Fed. Cir. 2014). Also, because
people adding floating point numbers “by hand” can generate intermediate
significand and exponent results using only pen and paper, step (a) is also
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abstract as reciting a mental process. 2019 Guidance, 84 Fed. Reg. at 52;
see also, e.g., Elec. Power Grp., LLC v. Alstom S.A., 830 F.3d 1350, 1354
(Fed. Cir. 2016) (“[W]e have treated analyzing information by steps people
go through in their minds, or by mathematical algorithms, without more, as
essentially mental processes within the abstract-idea category.”)
Step (b) uses the exponent of the intermediate result to determine a
“mask.” A mask is “a series of bits” used for processing binary data using
Boolean algebra. See Spec. ¶ 31 (identified at Appeal Br. 2 as the
Specification description corresponding to step (b)); see also MICROSOFT
COMPUTER DICTIONARY 329 (5th ed. 2002) (explaining, consistent
with Appellant’s Specification, that a mask is “[a] binary value used to
selectively screen out or let through certain bits in a data value” and
“[m]asking is performed by using a logical operator (AND, OR, XOR, or
NOT) to combine the mask and the data value”). An artisan of ordinary skill
would understand the recited determining step principally describes a
mathematical determination of the bit values of the mask, using the value of
the intermediate exponent. And, as with step (a), artisans of ordinary skill
can implement step (b) with only pen and paper. Thus, step (b) also recites
an abstract idea in the categories of both mathematical concepts and mental
processes. 2019 Guidance, 84 Fed. Reg. at 52.
Applying the mask in step (c) is an application of Boolean algebra.
Similar to the first two steps, this step is abstract in the categories of
mathematical concepts and mental processes. Id.
Step (d) uses the masked significand to create “an overflow condition
code.” “[O]verflow” is a technical term of art. See, e.g., MICROSOFT
COMPUTER DICTIONARY at 383 (explaining the relevant definition of
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overflow as “the condition that occurs when data resulting from input or
processing requires more bits than have been provided in hardware or
software to store the data” (e.g., “a floating-point operation whose result is
too large for the number of bits allowed for the exponent”)). The overflow
condition code indicates whether, based on the masked significand’s value,
the system’s capacity for representing numbers as binary data will be
exceeded because a value is too large to be represented by the number of bits
available. An artisan of ordinary skill can read (or define) the specifications
for a system to learn the capabilities for the number of bits the system can
handle when processing floating point numbers. With that knowledge, the
artisan can mentally perform the math (or with pen and paper) that will
determine if a value requires more bits than the system can handle, i.e.,
whether, based on a particular significand, an overflow condition will or will
not result for that system. Thus, as with steps (a)–(c), step (d) also recites an
abstract idea, in the categories of both a mathematical concept and a mental
process. 2019 Guidance, 84 Fed. Reg. at 52.
Accordingly, we proceed to prong two.
Alice/Mayo Step One, 2019 Guidance Step 2A Prong Two
We next consider whether, beyond the recited judicial exception,
claim 30 recites any additional elements that, individually or in combination,
integrate the judicial exception into a practical application. See 2019
Guidance, 84 Fed. Reg. at 54–55. It does: claim 30’s generation of an
overflow condition code by a processor based on intermediate results
generated during a floating point addition operation integrates the recited
abstract idea(s) into a practical application. The Specification explains how
claimed embodiments that include the described “anticipator 116” improve
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processor performance by determining that the values being used during a
floating point operation will cause an overflow or underflow conditions. See
Spec. ¶¶ 10, 26, 31–33. Because the claims “focus on a specific means or
method that improves” how a processor handles machine limitations that can
result in an overflow or underflow condition when operating on floating
point numbers, they are not “directed to a result or effect that itself is the
abstract idea and merely invoke generic processes and machinery.” McRO,
Inc. v. Bandai Namco Games Am. Inc., 837 F.3d 1299, 1314 (Fed. Cir. 2016)
(citations omitted). In other words, claim 30 improves (rather than merely
uses) computer technology. Thus, we agree with Appellant that
[t]he detection of the [ov]erflow condition is something that
helps the processor better function as a processor (specifically,
by avoiding overflow situations). The overflow condition [is]
not of any immediate interest other than to the processor
itself. . . . This is about operation of the computer itself.
Appeal Br. 12–13; see also Reply Br. 2–3.
Accordingly, claim 30 is not directed to a recited judicial exception.
Hence, we agree with Appellant the Examiner erred in rejecting claims 30–
38 under 35 U.S.C. § 101.
The § 103 Rejections
In rejecting claim 30, the Examiner relies on Rubanovich for teaching
the receiving and applying steps, both of which require an “intermediate
significand” that is part of “an intermediate result for an addition operation.”
Final Act. 8–9 (citing Rubanovich ¶¶ 30, 41, Figs. 2, 4). Appellant contends
the Examiner errs because, “[s]o far as Rubanovich discloses, the addition is
performed and there is no disclosure of intermediate results that occur after
the addition operation begins, but before it is finished.” Appeal Br. 14.
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The Examiner responds by explaining that in the fused multiply add
(FMA) module 103 illustrated in Rubanovich Figure 2, either the output of
shifter 205 or the output of multiplier 210 teaches the recited “intermediate
result for an addition operation” (the “disputed limitation”). Ans. 6–8.
Appellant replies that the Examiner interprets the disputed limitation too
broadly because, based on the plain meaning of intermediate, it requires
“that the result is obtained after the addition process begins, but before it
concludes.” Reply Br. 3–4.
Appellant’s argument is persuasive. “[T]he proper BRI construction
is not just the broadest construction, but rather the broadest reasonable
construction in light of the specification.” In re Man Mach. Interface Techs.
LLC, 822 F.3d 1282, 1287 (Fed. Cir. 2016); see also In re Am. Acad. of Sci.
Tech Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004). Here, the Specification
consistently describes embodiments of “intermediate results” for floating
point operations as results that are generated during performance of the
floating point operations, i.e., generated after the operation starts but before
it ends. See, e.g., Spec. ¶¶ 28–29; see also id. ¶ 4 (providing a consistent
summary of the invention). Ordinarily skill artisans would have understood,
in the context of claim 30 and in view of the Specification, that “an
intermediate result for an addition operation” describes (recites) a result that
is generated after the addition operation commences but before the addition
operation completes.
By using an overly broad interpretation, the Examiner errs in finding
Rubanovich teaches the disputed limitation. In Rubanovich, the outputs
from the shifter and multiplier are intermediate results within the FMA
module, and the FMA module includes a floating point addition module 105
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(and a carry save addition (CSA) module 215 that processes the shifter and
multiplier outputs prior to providing the inputs to the addition module). Vis-
à-vis addition operations, the FMA module’s outputs from the shifter and
multiplier are input data for addition operations, not intermediate results for
them, as recited.
Accordingly, we do not sustain the rejection of claim 30. For the
same reason we do not sustain the rejection of independent claim 36, which
recites a processor configured to perform the same steps as recited in claim
30, which stands rejected based on the same findings for claim 30, and
which Appellant argues together with claim 30. See Appeal Br. 14–15, 19
(Claims App’x); see also Final Act. 12. We also, accordingly, do not sustain
the rejection of dependent claims 31, 32, 37, and 38.
Independent claim 33 recites the same steps as claim 30, with one
exception: in lieu of “receiving . . . an intermediate result for an addition
operation,” claim 36 recites “receiving . . . an intermediate result for an
operation of converting an operand with a larger precision to a resultant with
a smaller precision.” Appeal Br. 18 (Claims App’x). In rejecting claim 33,
the Examiner relies on the same findings and reasoning as for claim 30, with
one exception: whereas for claim 30 the Examiner relies on Rubanovich for
teaching “an addition operation,” for claim 33 the Examiner relies on (a)
Rubanovich for teaching “an operation” (relying on the same disclosure in
Rubanovich cited in claim 30 for the addition operation) and (b) on Putrino
for teaching that the operation is “an operation of converting an operand
with a larger precision to a resultant with a smaller precision.” Compare
Final Act. 8–10 with 12–15.
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Appellant separately contends the Examiner errs in the § 103 rejection
of claim 33, presenting arguments similar to those presented for claim 30.
See Appeal Br. 15 (also contending the additionally cited reference (Putrino)
does not teach or suggest “intermediate results,” as recited). Appellant
persuades us the Examiner errs for essentially the same reasons discussed
above for claim 30, i.e., because the shifter and multiplier outputs in Figure
2 of Rubanovich are not “an intermediate result for an operation of
converting an operand,” as recited (and because there is no finding in the
record that Putrino cures this defect of Rubanovich). Accordingly, we do
not sustain the rejection of claim 33 or its dependent claims 34 and 35.
CONCLUSION
In summary:
Claim(s)
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
30–38 101 Eligibility 30–38
30–32,
36–38 103
Rubanovich, Gschwind,
Huck
30–32,
36–38
33–35 103 Rubanovich, Gschwind, Huck, Putrino 33–35
Overall
Outcome
30–38

REVERSED