International Business Machines CorporationDownload PDFPatent Trials and Appeals BoardMay 28, 202014317413 - (D) (P.T.A.B. May. 28, 2020) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 14/317,413 06/27/2014 Son T. Dao DE920140036US1 7966 11432 7590 05/28/2020 IBM Corporation - Endicott Drafting Center 11501 Burnet Road Austin, TX 78758 EXAMINER LAROCQUE, EMILY E ART UNIT PAPER NUMBER 2182 NOTIFICATION DATE DELIVERY MODE 05/28/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): edciplaw@us.ibm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte SON T. DAO and SILVIA MELITTA MUELLER Appeal 2019-004872 Application 14/317,413 Technology Center 2100 ____________ Before DEBRA K. STEPHENS, MICHAEL M. BARRY, and PHILLIP A. BENNETT, Administrative Patent Judges. BARRY, Administrative Patent Judge. DECISION ON APPEAL Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 33, 34, and 36–41, which are all of the pending claims.2 See Appeal Br. 11–19; see also Final Act. 1, 4–17. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 We use “Appellant” to refer to the “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies International Business Machines Corporation as the real party in interest. Appeal Br. 3. 2 Appellant filed an Amendment on July 7, 2018 (after the rejection but before filing the Appeal Brief) to cancel claim 35, which had been pending at the time of the rejection. The Examiner entered that cancellation into the record in an Advisory Action mailed Aug. 2, 2018. Appeal 2019-004872 Application 14/317,413 2 Introduction The Specification states the “invention relates generally to the field of floating point processing, and more particularly to determining overflow/ underflow conditions.” Spec. ¶ 1. Discussing the background of the invention, the Specification explains: Floating point numbers may be used to represent a large range of numbers using a limited number of bits. Floating point numbers act as if there is no fixed number of bits before or after the decimal point; that is, the decimal point can float. Floating point numbers are represented by a number value[3] and an exponent associated with that number value. Due to the added complexity of handling both a value and an exponent when performing calculations with floating point numbers, some processors comprise floating point processors. Floating point processors are specialized processors designed for performing floating point arithmetic, such as addition, subtraction, multiplication, division, bit shifting and other operations. While floating point numbers typically have larger ranges than integer number[s], the representations of floating point numbers still have limits based on the amount of storage used to store the representation. The limits of a floating point numbers representation are based primarily of the range of exponents that can be stored. When the exponent falls outside this range underflow or overflow occurs. Id. ¶ 2. Claim 33 is illustrative of the claims on appeal: 33. A method comprising: receiving, by a set of processor(s), an intermediate result for a subtraction operation, with the intermediate result including an intermediate significand and an intermediate exponent; 3 The number value maps to the “significand” in the claims. Appeal 2019-004872 Application 14/317,413 3 determining, by the processor(s) set, a mask based, at least in part, on the value of the intermediate exponent; applying, by the processor(s) set, the mask to the intermediate significand to obtain a masked significand; and generating, by the processor(s), an underflow condition code based, at least in part, a value of the masked significand. Appeal Br. 17 (Claims App’x). The Rejections4 The Examiner rejected claims 33, 34, and 39–41 under 35 U.S.C. § 103 as obvious over Rubanovich (US 2014/0379773 A1; Dec. 25, 2014), Gschwind (US 2013/0212139 A1; Aug. 15, 2013), and Huck (US 6,151,669; Nov. 21, 2000). Final Act. 9–13. The Examiner rejected claims 36–38 under § 103 as obvious over Rubanovich, Gschwind, Huck, and Putrino (US 5,805,475; Sept. 8, 1998). Final Act. 12–16. ANALYSIS In rejecting claim 33, the Examiner relies on Rubanovich for teaching the receiving and applying steps, both of which require an “intermediate significand” that is part of “an intermediate result for an subtraction operation.” Final Act. 9–10 (citing Rubanovich ¶¶ 30, 41, Figs. 2, 4). Appellant contends the Examiner errs because, “[s]o far as Rubanovich discloses, the subtraction is performed and there is no disclosure of 4 The Examiner’s Answer withdrew the rejection under 35 U.S.C. § 101 of claims 3, 34, and 39–41 (Ans. 3) and the rejection under 35 U.S.C. § 112(a) of claim 35 has been rendered moot by Appellant’s cancellation of that claim (see supra note 2). Appeal 2019-004872 Application 14/317,413 4 intermediate results that occur after the subtraction operation begins, but before it is finished.” Appeal Br. 14. The Examiner responds by explaining that in the fused multiply add (FMA) module 103 illustrated in Rubanovich Figure 2, either the output of shifter 205 or the output of multiplier 210 teaches the recited “intermediate result for the subtraction operation” (the “disputed limitation”). Ans. 4–6. Appellant replies that the Examiner interprets the disputed limitation too broadly because, based on the plain meaning of intermediate, it requires “that the result is obtained after the subtraction process begins, but before it concludes.” Reply Br. 2. Appellant’s argument is persuasive. “[T]he proper BRI construction is not just the broadest construction, but rather the broadest reasonable construction in light of the specification.” In re Man Mach. Interface Techs. LLC, 822 F.3d 1282, 1287 (Fed. Cir. 2016); see also In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004). Here, the Specification consistently describes embodiments of “intermediate results” for floating point operations as results that are generated during performance of the floating point operations, i.e., generated after the operation starts but before it ends. See, e.g., Spec. ¶¶ 28–29; see also id. ¶ 4 (providing a consistent summary of the invention). Ordinarily skill artisans would have understood, in the context of claim 30 and in view of the Specification, that “an intermediate result for a subtraction operation” describes (recites) a result that is generated after the subtraction operation commences but before the addition operation completes. By using an overly broad interpretation, the Examiner errs in finding Rubanovich teaches the disputed limitation. In Rubanovich, the outputs Appeal 2019-004872 Application 14/317,413 5 from the shifter and multiplier are intermediate results within the FMA module, and the FMA module includes a floating point addition module 105 (and a carry save addition (CSA) module 215 that processes the shifter and multiplier outputs prior to providing the inputs to the addition module). Vis- à-vis addition operations, the FMA module’s outputs from the shifter and multiplier are input data for addition operations, not intermediate results for them, as recited. Accordingly, we do not sustain the rejection of claim 33. For the same reason we do not sustain the rejection of independent claim 39, which recites a processor configured to perform the same steps as recited in claim 33, which stands rejected based on the same findings for claim 33, and which Appellant argues together with claim 33. See Appeal Br. 14–15, 19 (Claims App’x); see also Final Act. 13. We also, accordingly, do not sustain the rejection of dependent claims 34, 40, and 41. Independent claim 36 recites the same steps as claim 33, with one exception: in lieu of “receiving . . . an intermediate result for a subtraction operation,” claim 36 recites “receiving . . . an intermediate result for an operation of converting an operand with a larger precision to a resultant with a smaller precision.” Appeal Br. 18 (Claims App’x). In rejecting claim 36, the Examiner relies on the same findings and reasoning as for claim 33, with one exception: whereas for claim 33 the Examiner relies on Rubanovich for teaching “a subtraction operation,” for claim 36 the Examiner relies on (a) Rubanovich for teaching “an operation” (relying on the same disclosure in Rubanovich cited in claim 33 for the subtraction operation) and (b) on Putrino for teaching that the operation is “an operation of converting an Appeal 2019-004872 Application 14/317,413 6 operand with a larger precision to a resultant with a smaller precision.” Compare Final Act. 9–11 with 14–16. Appellant separately contends the Examiner errs in the § 103 rejection of claim 36, presenting arguments similar to those presented for claim 33. See Appeal Br. 15–16 (also contending the additionally cited reference (Putrino) does not teach or suggest “intermediate results,” as recited). Appellant persuades us the Examiner errs for essentially the same reasons discussed above for claim 33, i.e., because the shifter and multiplier outputs in Figure 2 of Rubanovich are not “an intermediate result for an operation of converting an operand,” as recited (and because there is no finding in the record that Putrino cures this defect of Rubanovich). Accordingly, we do not sustain the rejection of claim 36 or its dependent claims 37 and 38. CONCLUSION In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 33, 34, 39–41 103 Rubanovich, Gschwind, Huck 33, 34, 39–41 36–38 103 Rubanovich, Gschwind, Huck, Putrino 36–38 Overall Outcome 33, 34, 36–41 REVERSED Copy with citationCopy as parenthetical citation