INTERNATIONAL BUSINESS MACHINES CORPORATION

Patent Trials and Appeals Board

Mar 18, 2021

2019005975 (P.T.A.B. Mar. 18, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/982,001 12/29/2015 Hiroki Yanagisawa JP920150118US1
(163-1091)
7476
49267 7590 03/18/2021
Tutunjian & Bitetto, P.C.
401 Broadhollow Road
Suite 402
Melville, NY 11747
EXAMINER
PIERRE LOUIS, ANDRE
ART UNIT PAPER NUMBER
2127
NOTIFICATION DATE DELIVERY MODE
03/18/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@tb-iplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte HIROKI YANAGISAWA
___________

Appeal 2019-005975
Application 14/982,001
Technology Center 2100
____________

Before CARL W. WHITEHEAD JR., JEREMY J. CURCURI, and
JAMES B. ARPIN, Administrative Patent Judges.

ARPIN, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1–7 and 9–19, all of the pending claims. Final
Act. 2.2 Claims 8 and 20 are cancelled. Appeal. Br. 24, 29 (Claims App.).
We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42.
Appellant identifies the real party-in-interest as International Business
Machines Corporation. Appeal Br. 3.
2 In this Decision, we refer to Appellant’s Appeal Brief (“Appeal Br.,” filed
March 4, 2019) and Reply Brief (“Reply Br.,” filed August 7, 2019); the
Examiner’s Final Office Action (“Final Act.,” mailed October 24, 2018),
Advisory Action (“Adv. Act.,” mailed December 26, 2018), and Answer
(“Ans.,” mailed July 3, 2019); and the Specification (“Spec.,” filed
December 29, 2015). Rather than repeat the Examiner’s findings and
Appellant’s contentions in their entirety, we refer to these documents.
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STATEMENT OF THE CASE
The claimed methods, systems, and computer program products
“generally relate[] to maximizing the solution to the maximum satisfiability
problem (MAX SAT) in a computer implemented method and system.”
Spec. ¶ 1. The Specification explains:
The Boolean Satisfiability Problem, abbreviated as
“SAT”, is answered by finding an interpretation that satisfies a
given Boolean formula. The problem asks whether the variables
of a given Boolean formula can be consistently replaced by the
values TRUE or FALSE so that the formula evaluates to TRUE.
MAX SAT is an optimization version of SAT that is defined in
formulas expressed in Conjunctive Normal Form (CNF).
Whereas SAT tries to determine whether or not a satisfying
assignment exists, MAX SAT tries to find an assignment that
maximizes the satisfaction of the formula.
Id. ¶ 2.
As noted above, claims 1–7 and 9–19 are pending. Claims 1, 10, and
17 are independent. Appeal Br. 22–23 (claim 1), 24–25 (claim 10), 27–28
(claim 17) (Claims App.). Claim 1 recites, “[a] computer-implemented
method for reducing processing time and computational resources used by at
least one hardware processor to verify at least one component of a computer
system” (id. at 22 (emphases added)); claim 10 recites a system comprising a
memory and one or more hardware processors, implementing a method
substantially as recited in claim 1 (id. at 24); and claim 17 recites, “[a]
computer program product comprising a non-transitory computer readable
storage medium having program instructions” to perform a method
substantially as recited in claim 1 (id. at 27). Claims 2–7 and 9 depend
directly or indirectly from claim 1, claims 11–16 depend directly from claim
10, and claims 18 and 19 depend directly from claim 17. Id. at 22–28.
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Claim 1, reproduced below with disputed limitations emphasized, is
representative.
1. A computer-implemented method for reducing
processing time and computational resources used by at least one
hardware processor to verify at least one component of a
computer system, the method comprising:
verifying, by at least one hardware processor operatively
coupled to a computer memory, at least one component of a
computer system using an optimum solution to a general MAX
SAT instance obtained from an optimum solution to a MAX:
2SAT instance, the general MAX SAT instance being stored in
the computer memory and comprising a set of clauses containing
Boolean variables connected by disjunctions, wherein verifying
the at least one component of the computer system includes
obtaining the optimum solution to the general MAX SAT
instance from the optimum solution to the MAX 2SAT instance
by:
transforming, by at least one hardware processor, the
general MAX SAT instance into a MAX 3SAT instance by
converting the clauses in MAX SAT into sets of clauses of at
most 3 variables;
transforming, by the at least one hardware processor, the
MAX 3SAT instance into the MAX 2SAT instance by
converting the clauses in MAX 3SAT into sets of clauses of at
most 2 variables, the MAX 2SAT instance;
solving, by the at least one hardware processor, the MAX
2SAT instance by obtaining an optimum solution to the MAX
2SAT instance, including performing an algorithm based on half
integrality and persistency properties associated with the MAX
2SAT instance; and
recovering, by the at least one hardware processor, the
optimum solution to the general MAX SAT instance from the
optimum solution to the MAX 2SAT instance;
wherein, due at least in part to the perfom1ance of the
algorithm based on the half integrality and persistency
properties, recovering the optimum solution to the general MAX
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SAT instance from the optimum solution to the MAX 2SAT
instance reduces processing time and computational resources
used by the at least one hardware processor for verifying the at
least one component of the computer system by reducing
processing time and computational resources used by the at least
one hardware processor for recovering the optimum solution to
the general MAX SAT instance when compared to obtaining the
optimum solution to the general MAX SAT instance directly from
the general MAX SAT instance.
Id. at 22–23 (emphasis added). Claims 10 and 17 recite limitations
corresponding to the disputed limitations of claim 1.
REJECTION3
The Examiner rejects claims 1–7 and 9–19 under 35 U.S.C. § 112(a)
as lacking adequate written description. Final Act. 5–6.
We review the appealed rejection for error based upon the issues
identified by Appellant, and in light of the contentions and evidence
produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential). We address the rejection below.
ANALYSIS.
Lack of Written Description
As noted above, the Examiner rejects claims 1–7 and 9–19 as lacking
adequate written description. Final Act. 5–6. Specifically, the Examiner
finds that the Specification fails to provide adequate written description for
the disputed limitations of independent claim 1 and the corresponding

3 The Examiner withdraws rejections of claims 1–7 and 9–19 (1) under
35 U.S.C. § 101 as directed to patent ineligible subject matter, without
significantly more, and (2) under 35 U.S.C. § 112(b) as indefinite. Ans. 3;
see Final Act. 3–5, 6–7.
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limitations of independent claims 10 and 17. For the reasons given below,
we do not sustain the rejection for lack of written description.
35 U.S.C. § 112(a) requires that
The specification shall contain a written description of the
invention, and of the manner and process of making and using it,
in such full, clear, concise, and exact terms as to enable any
person skilled in the art to which it pertains, or with which it is
most nearly connected, to make and use the same, and shall set
forth the best mode contemplated by the inventor or joint
inventor of carrying out the invention.
(Emphasis added.) As our reviewing court has explained,
The “written description” requirement implements the
principle that a patent must describe the technology that is sought
to be patented; the requirement serves both to satisfy the
inventor’s obligation to disclose the technologic knowledge upon
which the patent is based, and to demonstrate that the patentee
was in possession of the invention that is claimed.
Capon v. Eshhar, 418 F.3d 1349, 1357 (Fed. Cir. 2005) (emphasis added).
Further, as Appellant correctly notes, Manual of Patent Examining
Procedure (MPEP)4 § 2163(I)(B) provides that “[w]hile there is no in haec
verba requirement, newly added claims or claim limitations must be
supported in the specification through express, implicit, or inherent
disclosure.” See Appeal Br. 13. To satisfy the written description
requirement, the Specification must describe the claimed invention in
sufficient detail that one skilled in the relevant art can reasonably conclude
that the inventor had possession of the claimed invention. Vas-Cath, Inc. v.
Mahurkar, 935 F.2d 1555, 1562–63 (Fed. Cir. 1991); see Appeal Br. 13

4 All references to the MPEP are to the Ninth Edition, Revision 10.2019
(Last Revised June 2020).
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(quoting MPEP § 2163.02). Specifically, to have “possession,” the
Specification must describe the claimed invention in a manner
understandable to a person of ordinary skill in the relevant art and show that
the inventor actually invented the claimed invention. Vas-Cath, 935 F.2d at
1562–63; Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed.
Cir. 2010) (en banc).
The Examiner finds that the Specification fails to provide adequate
written description because:
The Examiner is unable to locate in the cited paragraph by the
applicant nor anywhere in the specification any supports for the
limitations that: “verifying ... at least one component of a
computer system using an optimum solution to a general MAX
SAT instance obtained from an optimum solution to a MAX
2SAT instance ... ”. Para 0066 which merely provides an
example how MAX SAT is used for model checking; however,
nowhere in the specification does it show that a solution to the
MAX SAT is used to verifying any model whatsoever.
Final Act. 6; see Adv. Act. 2; Ans. 4–5. We disagree.
Appellant contends the Specification discloses that MAX SAT may
be used for model checking, e.g., verification of hardware and software
systems. Reply Br. 5; see Appeal Br. 14–15. Specifically, the Specification
discloses:
There are numerous real world applications for MAX
SAT. For example, MAX SAT is used for model checking, e.g.,
verification of hardware and software systems. . . . By way of
example, an intelligent agent can be provided with the capability
of solving MAX SAT in accordance with present principles.
Spec. ¶ 66 (emphases added). Further, Appellant contends,
the independent claims recite sub-clauses, including the
transforming, solving and recovering steps, that are used to
obtain an optimum solution to a general MAX SAT instance
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from an optimum solution to a MAX 2SAT instance. That is, the
optimal solution is indeed obtained by the claims. Moreover,
such steps for obtaining the optimum solution are supported by,
e.g., FIGs. 2 and 3 and the corresponding portions of the present
specification. As discussed above, paragraph [0066] of the
present specification describes some examples of applications of
the optimum solution obtained by the claims, including model
checking (e.g., verification of at least one component of a
computer system).
Reply Br. 6–7; see Appeal Br. 15.
Appellant persuasively contends that the Specification, considered in
its entirety, discloses methods for “verifying at least one component of a
computer system using an optimum solution to a general MAX SAT
instance obtained from an optimum solution to a MAX 2SAT instance, as
recited in the independent claims.” Appeal Br. 14; Reply Br. 6; see Appeal
Br. 22 (Claims App.). Specifically, the Specification discloses a method of
obtaining an optimum solution to a general MAX SAT instance from an
optimum solution to a MAX 2SAT instance, via the intervening steps of
transforming the MAX SAT instance into a MAX 3SAT instance and then
into a MAX 2SAT instance (see, e.g., Spec. ¶¶ 24, 37–40, 60–62); and the
Specification further discloses numerous examples of “real world
applications for MAX SAT,” including verifying computer hardware, in
which the disclosed methods may be used to solve the general MAX SAT
instance (id. ¶ 66). We find the Examiner’s narrow focus on the
Specification’s disclosure in Paragraph 66 and the Examiner’s search for an
in haec verba recitation of the disputed limitations contrary to our reviewing
court’s standards for assessing the adequacy of written description. E.g.,
Final Act. 6 (“If Applicant feels otherwise, the Examiner respectfully invites
the Applicants to point to specific portion of the original specification with
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very clear explanation where and how this limitation is disclosed as
claimed.”).
On this record, we are persuaded the Examiner errs in finding that
independent claim 1, as well as claims 10 and 17, which recite
corresponding disputed limitations, lacks adequate written description, and
we do not sustain the rejection of those claims. Because the Examiner relies
solely on its findings with respect to the independent claims to reject the
dependent claims, we also do not sustain the rejection of those claims as
lacking adequate written description. See Appeal Br. 21; Reply Br. 7.
DECISION
1. The Examiner errs in rejecting claims 1–7 and 9–19 under 35 U.S.C.
§ 112(a) as lacking adequate written description.
2. Thus, on this record, claims 1–7 and 9–19 are not unpatentable.
CONCLUSION
We reverse the Examiner’s rejection of claims 1–7 and 9–19.
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1–7, 9–19 112(a) Written Description 1–7, 9–19

REVERSED