2020000337 (P.T.A.B. Apr. 30, 2021)

Intel Corporation

Patent Trials and Appeals BoardApr 30, 2021

2020000337 (P.T.A.B. Apr. 30, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/873,089 01/17/2018 Mahesh Natu ITL.2138C1US P30716D2-C1 4992 47795 7590 04/30/2021 TROP, PRUNER & HU, P.C. PO Box 41790 HOUSTON, TX 77241 EXAMINER MEHTA, JYOTI ART UNIT PAPER NUMBER 2182 NOTIFICATION DATE DELIVERY MODE 04/30/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): Inteldocs_docketing@cpaglobal.com tphpto@tphm.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte MAHESH NATU, THANUNATHAN RANGARAJAN, GAUTAM DOSHI, SHAMANNA M. DATTA, BASKARAN GANESAN, MOHAN J. KUMAR, RAJESH S. PARTHASARATHY, FRANK BINNS, RAJESH NAGARAJA MURTHY, ROBERT C. SWANSON ____________________ Appeal 2020-000337 Application 15/873,089 Technology Center 2100 ____________________ Before ALLEN R. MacDONALD, BRADLEY W. BAUMEISTER, and KALYAN K. DESHPANDE, Administrative Patent Judges. MacDONALD, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1–17 and 19. Appeal Br. 7. Claim 18 is cancelled. March 28, 2019 Amendment 5. We have jurisdiction under 35 U.S.C. § 6(b). We reverse, and we enter a new ground of rejection. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest is Intel Corporation. Appeal Br. 3. Appeal 2020-000337 Application 15/873,089 2 CLAIMED SUBJECT MATTER Claim 1 is illustrative of the claimed subject matter (emphasis, formatting, and bracketed material added): 1. A processor comprising: [A.] a plurality of cores formed on a single semiconductor die; [B.] decode circuitry of at least one core to decode instructions of one or more threads; [C.] execution circuitry of the at least one core to perform out- of-order execution of the instructions of the one or more threads; [D.] the execution circuitry to execute system management mode (SMM) handler code from a designated system memory address region to perform system management operations in response to a system management interrupt (SMI); [E.] save/restore circuitry to save at least a portion of a first execution state of a first thread to a cache prior to entering the SMM; and [F.] the execution circuitry to execute a resume instruction included in the SMM handler code to cause the save/restore circuitry to restore the at least a portion of the first execution state from the cache upon exiting the SMM; [G.] wherein the processor does not invalidate the cache responsive to entering or exiting the SMM.2 2 Appellant claims priority to US 10,169,268 B2, US 9,465,647 B2, and US 8,578,138 B2. However, we find insufficient 35 U.S.C. § 112(a) written description support for limitation [G] in these patents. At best, each patent merely states at column 7 of each: Certain instruction set architectures (ISAs) include instructions such as a write back and invalidate instruction (e.g., wbinvd), which invalidates all cache lines and writes them back to memory. These operations can take a long time to complete . . . . In one embodiment, any flow that will delay SMM entry by more than 5 microseconds can Appeal 2020-000337 Application 15/873,089 3 REFERENCES3 The Examiner and this Panel rely on the following references: Name Reference Date Yuen US 5,357,628 Oct. 18, 1994 Beck US 5,826,101 Oct. 20, 1998 Neiger US 2007/0005870 A1 Jan. 4, 2007 Yamasaki US 2007/0022428 A1 Jan. 25, 2007 Arimilli US 2007/0081516 A1 Apr. 12, 2007 Vasudevan US 2007/0156960 A1 July 5, 2007 Bilski US 7,380,106 B1 May 27, 2008 This Panel cites the following additional reference: Name Reference Date Lovelace US 7,107,405 B2 Sept. 12, 2006 REJECTIONS A. The Examiner rejects claims 1–4, 6, and 19, under 35 U.S.C. § 103(a) as being unpatentable over the combination of Yuen, Yamasaki, Vasudevan, and Bilski. Final Act. 3–9. We select claims 1 and 2, as the representative claims for this rejection. Appellant does not present separate arguments for claims 3, 4, 6, be termed as a long flow. With regard to SMM, if one or more logical processor is in a long flow, it delays SMM entry. Notwithstanding this concern, we and the Examiner have used prior art that is earlier than the earliest claimed priority date nonetheless. 3 All citations herein to patent and pre-grant publication references are by reference to the first named inventor only. Appeal 2020-000337 Application 15/873,089 4 and 19. Thus, the rejection of these claims turns on our decision as to claim 1. Except for our ultimate decision, we do not discuss the merits of the Examiner’s § 103(a) rejection of claims 3, 4, 6, and 19 further herein. B. The Examiner rejects claims 7–10 and 12–16, under 35 U.S.C. § 103(a) as being unpatentable over the combination of Yuen, Yamasaki, and Vasudevan. Final Act. 9–17. The Examiner rejects claim 5 under 35 U.S.C. § 103(a) as being unpatentable over the combination of Yuen, Yamasaki, Vasudevan, Bilski, and Arimilli. Final Act. 17. The Examiner rejects claim 11 under 35 U.S.C. § 103(a) as being unpatentable over the combination of Yuen, Yamasaki, Vasudevan, and Arimilli. Final Act. 18. The Examiner rejects claim 17 under 35 U.S.C. § 103(a) as being unpatentable over the combination of Yuen, Yamasaki, Vasudevan, Bilski, and Neiger. Final Act. 18–19. The Examiner rejects claim 17 under 35 U.S.C. § 103(a) as being unpatentable over the combination of Yuen, Yamasaki, Vasudevan, Bilski, and Beck. Final Act. 19–20. To the extent that Appellant discusses claims 5 and 7–17, Appellant merely repeats or references the arguments directed to claim 1. Appeal Br. 10–12. Such a referenced argument (or repeated argument) is not an argument for “separate patentability.” Thus, the rejections of these claims turn on our decision as to claim 1. Except for our ultimate decision, we do not address the merits of the § 103(a) rejections of claims 5 and 7–17 further herein. Appeal 2020-000337 Application 15/873,089 5 OPINION We have reviewed the Examiner’s rejections in light of Appellant’s Appeal Brief and Reply Brief arguments. A. Appellant raises the following argument in contending that the Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a). [A]s described in FIG. 2 of Yuen, in response to an SMI, a SMRAM space is switched into a part of a system memory space and a system state of the system is saved into this SMRAM space. Yuen however fails to teach that this space is present in its processor. Instead, it is a separate memory. Yuen, column 4, lines 12–15. As a further matter, Yuen in fact teaches that for SMM operation, it is important that this memory remain external to the processor: “by keeping system memory 44 and the system management memory 48 separate and external, the present invention may be practiced with the added advantage of debugging system memory 44 failures.” Yuen, column 4, lines 30-34. Thus not only does Yuen not teach as contended, in fact Yuen actually operates contrary to the contended manner. Appeal Br. 8 (emphasis added). We are unpersuaded by Appellant’s argument. As pointed out by the Examiner, Appellant’s argument cites to Yuen at column 4, lines 12–15 and lines 30–34, but overlooks that this argument is contradicted by column 4, lines 23–30. Although the system memory 44 and the system management memory 48 are shown to be separate and external to the basic components GENCPU, GENIO and GENVGA of the exemplary microprocessor based computer system 10, it will be appreciated that the system memory 44 as well as the system Appeal 2020-000337 Application 15/873,089 6 management memory 48 may be integrated and/or internal to the one of the basic component, for example GENCPU. Yuen, col. 4:23–30. We agree with the Examiner’s reasoning. We also adopt the Examiner’s response (Ans. 3–4) with which we agree. In addition, contrary to Appellant’s argument, we do not find in claim 1 any requirement that the argued space (cache) be present in the processor. Rather, claim 1 requires that the “save/restore circuitry” be part of the processor and that it saves “to a cache.” However, we find claim 1 to be silent as to the location of the cache (i.e., an external location is not precluded). B. Also, Appellant raises the following argument in contending that the Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a). [T]he Examiner relies on the additional reference Yamasaki for the contended cache memory. However, Yamasaki is directed to context switches between regular, non-SMM threads. In fact, Yamasaki nowhere even mentions SMM or the capability of its cache to store state in the context of SMM operations. The plain matter is that Yamasaki only teaches context switches between different run-time OS threads. Yamasaki, paragraph 7. Regarding this combination of Yamasaki and Yuen, one of skill in the art simply would not combine their teachings. In this regard, Yamasaki is directed to switching of context between different user-level threads, namely different OS threads, such as of a real-time OS. Yamasaki, paragraph 1. Appeal Br. 8. [E]ven when these references are combined, the arrangement set forth in claim 1 fails to be taught or suggested. And, for the reasons above, one of skill in the art simply would not be motivated to make the combination between the two Appeal 2020-000337 Application 15/873,089 7 references. Even if it were to occur, the combination does not result in the recited subject matter of the claim. As a further matter, somehow modifying these references would violate the secure aspect of SMM by using user-visible OS thread switching techniques, thus changing the principle of operation of the reference in contravention of well-established patent law. M.P.E.P. § 2143.01(VI). Appeal Br. 10. We are unpersuaded by Appellant’s arguments. We agree with the Examiner’s response set forth at page 5 of the Examiner’s Answer. Appellant does not address the actual reasoning of the Examiner’s rejection. Instead, Appellant attacks the Yamasaki reference singly for lacking a teaching that the Examiner relied on a combination of Yuen and Yamasaki to show. In particular, the rejection does not rely on Yamasaki for teaching the “cache to store state in the context of SMM operations” aspect disputed by Appellant. Rather, the Examiner relied on Yuen to show “store state in the context of SMM operations” (Final Act. 4), and relied on Yamasaki to show it was known to use a cache to store a state (Final Act. 4). The Examiner then reasoned that it would have been obvious to modify the pre-exiting operation of Yuen to include a cache as in Yamasaki. Final Act. 5. One cannot show nonobviousness by attacking references individually when the rejection is based on a combination of references. In re Merck & Co. Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986); see also In re Keller, 642 F.2d 413, 425 (CCPA 1981) (explaining the relevant inquiry is whether the claimed subject matter would have been obvious to those of ordinary skill in the art in light of the combined teachings of those references). Appeal 2020-000337 Application 15/873,089 8 C. Appellant raises the following argument in contending that the Examiner erred in rejecting claim 2 under 35 U.S.C. § 103(a). The rejection should be reversed for at least the same reasons above as to claim 1. The rejection should further be reversed, as the basis for the rejection fails to present any teaching or suggestion of saving thread execution state in cache lines which map to a SMRAM address region. Here, the Examiner refers to FIGS. 1 and 2 of Yamasaki and its paragraphs 54, 57 and 60. Yet all that Yamasaki teaches in these aspects is that data and instructions are obtained from an external memory. When a context switch occurs, data from registers are stored through the cache memory and to the external memory and vice-versa. Nevertheless, this says nothing as to any type of saving in cache lines which map to a SMRAM address region. Instead, the entire discussion of Yamasaki is devoid of any mention of SMM or SMRAM. Appeal Br. 11 (emphasis omitted). We are unpersuaded by Appellant’s arguments for the reasons set forth supra. Additionally, we agree with the Examiner’s response set forth at pages 10–11 of the Examiner’s Answer. D. Further, Appellant raises the following argument in contending that the Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a). [T]here is no reference support [in Yamasaki] to not invalidating a cache responsive to entering or exiting SMM -- it simply nowhere appears in that reference. Here the Examiner ascribes this ability simply as a result of combining these two [Yuen and Yamasaki] references, without any support from either reference. Final Office Action, page 5. Appeal Br. 9 (emphasis added). Appeal 2020-000337 Application 15/873,089 9 We agree with Appellant’s argument. Based on this argument, the Examiner’s reasoning of the Final Rejection and Answer is not sufficient to show that the combination alone renders obvious claim 1. However, we nonetheless deem Appellant’s claimed invention to be unpatentable under 35 U.S.C. §103(a). The feature recited by claim 1 of “not invalidating the cache responsive to entering or exiting the SMM” was known to a person of ordinary skill in the art in question at the time of the invention. Evidence of this is found in the Lovelace patent (US 7,107,405 B2) at column 2, line 14 through column 4, line 3. Particularly, Lovelace discloses: In certain embodiments, a Cache Line Flush instruction (CLFLUSH) may be used by BIOS to force a single cache-line eviction without affecting other cache contents. . . . In one embodiment BIOS may use CLFLUSH to evict all cache lines containing SMM memory secrets before allowing the processor to leave the SMM context. . . . In one embodiment, a CLFLUSH instruction may be used to provide desired cache lines to SMM memory. Alternately, in other embodiments a flush of the entire cache may be performed for example, using a Write Back and Invalidate Cache instruction (e.g. WBINVD). However, such a global flush may cause more significant latencies. . . . In one embodiment, a CLFLUSH instruction may be used to write the modified cache lines to SMM memory. However in other embodiments, a WBINVD instruction or other such instruction to invalidate and flush the cache may be used. . . . In one embodiment, a CLFLUSH instruction may be used to write the desired line or lines to SMM memory. Alternately in other embodiments a WBINVD or other such instruction may be used. Lovelace, column 2, line 14 through column 3, line 56 (emphasis added). Appeal 2020-000337 Application 15/873,089 10 Appellant’s Specification discloses that the “write back and invalidate instruction (e.g., wbinvd), which invalidates all cache lines and writes them back to memory,” is problematic because “it delays SMM entry.” Spec. 29. Appellant then recites at claim 1 a requirement that “the processor does not invalidate the cache responsive to entering or exiting the SMM.” We find that a CLFLUSH instruction is a known non-invalidation alternative for the cache invalidating WBINVD instruction, and we conclude it would have been obvious to substitute one for the other. E. Based on the Examiner’s § 103(a) rejections and the above reasons, we designate our reversal of the Examiner § 103(a) rejections as new grounds of rejection under 35 U.S.C. § 103(a), on each basis set forth by the Examiner in further combination with the assignee’s Lovelace patent. CONCLUSION Appellant has demonstrated the Examiner erred in rejecting claims 1–17 and 19 as being unpatentable under 35 U.S.C. § 103(a). The Examiner’s rejections of claims 1–17 and 19 as being unpatentable are reversed. We newly reject claims 1–17 and 19 under 35 U.S.C. § 103(a) as being unpatentable. DECISION SUMMARY In summary: Claim(s) Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed New Ground 1–4, 6, 19 103(a) Yuen, Yamasaki, Vasudevan, Bilski 1–4, 6, 19 Appeal 2020-000337 Application 15/873,089 11 7–10, 12– 16 103(a) Yuen, Yamasaki, Vasudevan 7–10, 12– 16 5 103(a) Yuen, Yamasaki, Vasudevan, Bilski, Arimilli 5 11 103(a) Yuen, Yamasaki, Vasudevan, Arimilli 11 17 103(a) Yuen, Yamasaki, Vasudevan, Bilski, Neiger 17 17 103(a) Yuen, Yamasaki, Vasudevan, Bilski, Beck 17 1–4, 6, 19 103(a) Yuen, Yamasaki, Vasudevan, Bilski, Lovelace 1–4, 6, 19 7–10, 12– 16 103(a) Yuen, Yamasaki, Vasudevan, Lovelace 7–10, 12– 16 5 103(a) Yuen, Yamasaki, Vasudevan, Bilski, Arimilli, Lovelace 5 11 103(a) Yuen, Yamasaki, Vasudevan, Arimilli, Lovelace 11 17 103(a) Yuen, Yamasaki, Vasudevan, Bilski, Neiger, Lovelace 17 17 103(a) Yuen, Yamasaki, Vasudevan, Bilski, Beck, Lovelace 17 Overall Outcome 1–17, 19 1–17, 19 Appeal 2020-000337 Application 15/873,089 12 TIME PERIOD FOR RESPONSE This decision contains a new ground of rejection pursuant to 37 C.F.R. § 41.50(b). 37 C.F.R. § 41.50(b) provides “[a] new ground of rejection pursuant to this paragraph shall not be considered final for judicial review.” 37 C.F.R. § 41.50(b) also provides that Appellant, WITHIN TWO MONTHS FROM THE DATE OF THE DECISION, must exercise one of the following two options with respect to the new ground of rejection to avoid termination of the appeal as to the rejected claims: (1) Reopen prosecution. Submit an appropriate amendment of the claims so rejected or new Evidence relating to the claims so rejected, or both, and have the matter reconsidered by the examiner, in which event the proceeding will be remanded to the examiner. . . . (2) Request rehearing. Request that the proceeding be reheard under § 41.52 by the Board upon the same Record. . . . Further guidance on responding to a new ground of rejection can be found in the Manual of Patent Examining Procedure § 1214.01. REVERSED; 37 C.F.R. 41.50(b)