Intel Corporation

Patent Trials and Appeals Board

Jul 30, 2021

2020003401 (P.T.A.B. Jul. 30, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/279,007 05/15/2014 Manoj R. Sastry P63163 7483
152398 7590 07/30/2021
Alliance IP, LLC - I
20 E. Thomas Rd.
Suite 2200, PMB 96
Phoenix, AZ 85012
EXAMINER
DEBNATH, SUMAN
ART UNIT PAPER NUMBER
2495
NOTIFICATION DATE DELIVERY MODE
07/30/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docket@allianceip.com
eofficeaction@appcoll.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
_______________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________

Ex parte MANOJ R. SASTRY, ENRICO D. CARRIERI,
MICHAEL NEVE DE MEVERGNIES, IOANNIS T. SCHOINAS, and
MICHAEL J. WIZNEROWICZ
_______________

Appeal 2020-003401
Application 14/279,007
Technology Center 2400
_______________

Before ALLEN R. MacDONALD, JASON V. MORGAN, and
MICHAEL R. ZECHER, Administrative Patent Judges.

MacDONALD, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE1
Pursuant to 35 U.S.C. § 134(a), Appellant2 appeals from the
Examiner’s decision to reject claims 1–20 (all pending claims). Appeal
Br. 1. We have jurisdiction under 35 U.S.C. § 6(b).

1 Unless otherwise noted, all references herein are to the Appeal Brief filed
on July 2, 2019.
2 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42(a). Appellant identifies the real party in interest is Intel
Corporation. Appeal Br. 2.
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We AFFIRM.
CLAIMED SUBJECT MATTER
Claim 1 is illustrative of the claimed subject matter (emphasis,
formatting, and bracketed material added):
1. An apparatus comprising:
[A.] a policy generator computing block comprising a
processor and logic, executable by the processor to:
[i.] identify, from lifecycle data, a particular one of a
plurality of defined lifecycle stages applicable to a
system-on-chip (SoC), wherein the lifecycle data
comprises a code to identify the particular lifecycle
stage and the value of the code is to be
progressively changed as the SoC progresses
through the plurality of lifecycle stages;
[ii.] identify a particular user;
[iii.] authenticate the particular user to debug the SoC;
[iv.] determine a particular policy based on the
particular lifecycle stage and identification of the
particular user, wherein a different policy is to be
applied for the particular user in at least one other
of the plurality of lifecycle stages; and
[B.] a transmitter to send policy data to at least one other
computing block of the SoC, wherein the policy data is
to identify the particular policy, and debug access by
the particular user at the other computing block is based
on the particular policy.
Appeal Br. 15, Claims App.
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REFERENCES3
The Examiner relies on the following references:
Name Reference Date
Giordano US 2009/0204823 A1 Aug. 13, 2009
Youm US 2010/0332783 A1 Dec. 30, 2010
Cho US 2011/0119744 A1 May 19, 2011
Anderson US 2011/0125894 A1 May 26, 2011
Kwidzinski US 2013/0346660 A1 Dec. 26, 2013

REJECTIONS
A. § 102 - Youm4
The Examiner rejects claims 1–7, 9, 11, 13–17, 19, and 20 under
35 U.S.C. § 102(a)(1) as being anticipated by Youm. Final Act. 3–15.5
We select claim 1 as the representative claim for this rejection.
Appellant does not present separate arguments for claims 2–7, 9, 11, 13–17,
19, and 20. Thus, the rejection of these claims turn on our decision as to
claim 1. Except for our ultimate decision, we do not address the merits of
this § 102 rejection of claims 2–7, 9, 11, 13–17, 19, and 20 further herein.

3 All citations herein to patent and pre-grant publication references are by
reference to the first named inventor only.
4 As we agree with the Examiner’s § 102 rejection of claims 1–7, 9, 11, 13–
17, 19, and 20 based on Youm, we do not reach the Examiner’s alternative
§ 103 rejection (Final Act. 6, 10, 11, 14, 15) of these claims based on the
combination of Youm and Cho. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed.
Cir. 2009) (not reaching other grounds of unpatentability after affirming a
ground based on anticipation).
5 All references herein are to the Final Action mailed on August 27, 2018.
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B. § 103
The Examiner rejects claims 8, 10, 12, and 18, under 35 U.S.C. § 103
as being unpatentable over various combinations of Youm, Cho, Giordano,
Kwidzinski, and Anderson. Final Act. 15–18.
To the extent that Appellant discusses claims 8, 10, 12, and 18,
Appellant merely refers to the arguments directed to claim 1. Appeal Br. 13.
Such a referenced argument (or repeated argument) is not an argument for
“separate patentability.” Thus, the rejections of these claims turn on our
decision as to claim 1. Except for our ultimate decision, we do not address
the merits of the § 103 rejections of claims 8, 10, 12, and 18 further herein.

OPINION
We have reviewed the Examiner’s rejections in light of Appellant’s
Appeal Brief and Reply Brief arguments.
A. Claim 1 – First Argument
Appellant raises the following argument in contending that the
Examiner erred in rejecting claim 1 under 35 U.S.C. § 102(a)(1) as being
anticipated by Youm.
Appellant notes:
[T]he Office explicitly concedes that[:]
Youm may not explicitly disclose ‘the value of the
code is to be progressively changed as the SoC
progresses through the plurality of lifecycle stages’;
and ‘wherein a different policy is to be applied for
the particular user in at least one other of the
plurality of lifecycle stages.’
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Final Action at p. 5. The Office attempts to justify the assertion
that the claims are allegedly anticipated by Youm based on the
allegation[:]
that these limitations essentially represent intended
use recitations. They do not further limit any
structure within the claimed apparatus or further
restrict or limit any method step within the claimed
method.
See id.
Appeal Br. 8 (formatting added).
While the code recited in the claims can be involved in later uses
(e.g., changing the value of the code to correspond to a change in
lifecycle stage), these recitations do, in fact, articulate structural
and functional aspects of the code, as well as the solution itself.
Accordingly, these limitations should be given patentable
weight. Specifically, a code that may be changed is itself a
changeable value (i.e., rather than a fixed, preset value, such as
the passwords and hash values discussed in Youm) and is a value
tied to (changing) status of an SoC device under development
(also unlike Youm which is agnostic to such changes). Likewise,
debug access policies applied by a computing block, which
depend on such changing code values, may be dynamically
adjusted in accordance with changes in the determine lifecycle
change of an SoC device. As such, the changeable nature of the
lifecycle data is directly responsible for the responsive
functionality of the policy generator block. Indeed, the
changeable nature of the lifecycle stage codes are one of the
foundational aspects of the claimed solution and system.
Appeal Br. 8–9 (emphasis added).
Youm is silent regarding lifecycle stages of a SoC device (in any
context), much less identifying, from lifecycle data, which of a
plurality of lifecycle stages applies to a corresponding SoC
device, or determining a debug access policy for the SoC device
based on the current lifecycle stage of the SoC. The Final Action
asserts that the “hash value” (or “HV”) discussed in Youm
allegedly discloses lifecycle data to be used to determine a debug
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policy to be applied at an SoC device. See, e.g., Final Action at
p. 3. Appellant disagrees.
Appeal Br. 9.
We are unpersuaded by Appellant’s argument. Essentially, Appellant
argues that (a) above limitation A.i. of claim 1 requires the real-time
determination of a system-on-chip’s (SoC) actively changing lifecycle stage,
and (b) Youm is silent regarding lifecycle stages of a SoC device (in any
context). We disagree.
First, we determine that the language of limitation A.i. of claim 1 is
not so limiting as it also is descriptive of prior to chip operation, identifying
and storing lifecycle data for plural lifecycle stages where the lifecycle data
differs for the plural lifecycle stages (i.e., progressively changes). Contrary
to Appellant’s assertion that Youm is silent as to such lifecycle stages,
paragraph 53 of Youm discloses a manufacturer (SL4) and plural other users
(SL3, SL2, SL1) whose hash values (i.e., passwords (PW3, PW2, PW1))
“are sequentially calculated.” We also determine that an ordinarily skilled
artisan would have understood the manufacturer and the plural other users to
represent at least two lifecycle stages of the SoC. Further, we do not find
Youm’s hashing operation to be limited to solely identifying a user. Rather,
the hashing operation identifies (a) a user (based on a password) and (b)
identifies an access level (based on the number of times the hashing
operation occurs). Indeed, Youm discloses the following:
The password (PW3) provided to the user (SL3) is the
hash value obtained by operating the password (PW 4) set by the
user (SL4) having the highest access level 4 one time. The
password (PW2) provided to the user (SL2) is the hash value
obtained by operating the password (PW4) two times and the
password (PW1) provided to the user (SL1) is the hash value
obtained by operating the password (PW4) three times.
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Youm ¶ 54. Given that the manufacturer and the plural other users are
assigned distinct access levels, we find that Youm discloses identifying a
particular one of a plurality of defined lifecycle stages. Furthermore, Youm
discloses a soft lock signal from fuse 310 that either, if low, allows access to
all regions of memory 130 or, if high, outputs an access level signal in
response to an inputted password. Id. ¶¶ 37–38, 41, 48. This fuse-driven soft
lock signal teaches claimed lifecycle data, which defines a first lifecycle
stage when all accesses to regions of memory are allowed (e.g., to allow pre-
deployment access by the manufacturer) and a first lifecycle state when
accesses to regions of memory are limited (e.g., to provide for security once
the semiconductor device is deployed to its users). Ans. 7.
Second, even if we agree with Appellant that the language of
limitation A.i. of claim 1 requires the real-time determination of a system-
on-chip’s (SoC) actively changing lifecycle stage. We agree with the
Examiner determination that the argued limitations represent intended use
recitations. These limitations do not further limit any structure within the
claimed apparatus or further restrict or limit any method step within the
claimed method. For example, the language of “wherein” limitation A.iv.
of claim 1 requires no more than Youm assigning SL4 (manufacturer) and
SL1 (4th user) to the manufacturer such that “a different policy is to be
applied for the particular user in at least one other of the plurality of
lifecycle stages.”
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B. Claim 1 – Second Argument
Also, Appellant raises the following argument in contending that the
Examiner erred in rejecting claim 1 under 35 U.S.C. § 102(a)(1) as being
anticipated by Youm.
Nowhere does Youm teach or suggest that a hash value
“identifies” a debugging area. Instead, the hash values in Youm
are ultimately based on “arbitrary” password inputs and have, by
themselves, no connection to lifecycle stages or even specific
“debugging areas,” as the Final Action submits. Accordingly,
neither the reference hash (HV) nor the hash value output for a
submitted password (HOPW) identify a debugging area.
Instead, Youm validates passwords by checking to determine if
the password is valid or not, and determining which “access
level” corresponds to the password (if it is determined to be
valid). See Youm . . . ¶¶ 0040, 41, 52. The access level can then
be determined (i.e., solely from the user’s password (e.g., the
user’s identity)), which may affect which “memory regions” the
user is able to access through a JTAG interface. See ¶¶ 0031-33,
41, 44, 45, etc. It cannot be said that the reference hash value
(HV) or the hash value output for a submitted password
(HOPW), discussed in Youm, identify a debugging area of a chip
(much less resources dependent on the lifecycle stage of the
chip). This is unsurprising, as Youm includes no discussion or
allusion to SoC device lifecycle stages.
Appeal Br. 10 (emphasis added).
Again, we are unpersuaded by Appellant’s argument. First, the term
“debugging area” does not appear in claim 1 (or any other pending claim).
Claim 1 only recites identifying “debug access” (limitation B. of claim 1).
See In re Self, 671 F.2d 1344, 1348 (CCPA 1982) (explaining that
limitations not appearing in the claims cannot be relied upon for
patentability).
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Second, as we discuss above, we find that Youm discloses identifying
an access level (based on the number of times the hashing operation occurs).
Youm further discloses that the access level of a user is the level of debug
access of the user. Youm ¶¶ 4–5, 17, 26–28.
C. Claim 1 – Third Argument
Further, Appellant raises the following argument in contending that
the Examiner erred in rejecting claim 1 under 35 U.S.C. § 102(a)(1) as being
anticipated by Youm.
[A]s recited in the claims, a debug policy is to be determined
based on a combination of a user identification and the current
lifecycle stage determined for the SoC device. However, Youm
explicitly sets forth that its “hash values” are derived from user
passwords. See, e.g., Youm . . . ¶¶ 0043, 46, 56, etc. The Youm
hash function does not add information to its inputs. In other
words, the Youm hash values are used to identify particular users
and include the exact same information as the password itself
(i.e., the corresponding user’s identity). The hashing scheme of
Youm (i.e., generating different hash outputs depending on the
number of times the hash function is applied before arriving at a
valid result) represents a clever solution to avoid explicitly
mapping individual passwords to access levels (e.g., as opposed
to a table mapping), but still does not affect the actual
information in the resulting hash values. This notwithstanding,
the Final Action tries to have it both ways-sometimes the
password/hash value are cited as reading on identifying the
particular user (see Final Action at p. 4), other times it allegedly
“uniquely identifies a particular debugging area” (see Final
Action at p. 3).
Appeal Br. 11.
We are unpersuaded by Appellant’s argument for the reasons already
discussed above. Also, at paragraphs 32 and 56, Youm discloses the
following:
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In this embodiment, each of the memory regions (MB1,
MB2, . . . , MBn) can be accessed by various users (SL1, SL2,
. . . , SLn) having different access levels from one another. For
example, the memory region (MB1) can be accessed by all the
users (SL1, SL2, . . . , SLn) who pass a password certification.
. . . The users (SLl, SL2, . . . , SLn) having a phased access level
receive different passwords and can be authorized to access to
the memory regions (MBl, MB2, . . . , MBn) by inputting the
received password.
Youm ¶ 32.
For example, when a password (PW) inputted in the secure
JTAG controller 320 is the password (PW3) provided to the user
(SL3), a hash value obtained through three times hash operations
in the hash operator 330 with respect to the inputted password
coincides with the hash value (HV) stored in the fuse 310.
Therefore, if the count value (CNT) is 3 when the hash value
(HOPW) outputted from the hash operator 330 coincides with the
hash value stored in the fuse 310, an access level is 3 and an
access level signal (AL[i:0]) is outputted as ‘0011’.
Youm ¶ 56.
D.
We agree with the Examiner’s determination that Youm anticipates
the subject matter of claim 1.
CONCLUSION
The Examiner has not erred in rejecting claims 1–7, 9, 11, 13–17, 19,
and 20 as being anticipated by Youm under 35 U.S.C. § 102(a)(1).
The Examiner has not erred in rejecting claims 8, 10, 12, and 18 as
being unpatentable under 35 U.S.C. § 103.
The Examiner’s rejection of claims 1–7, 9, 11, 13–17, 19, and 20 as
being unpatentable under 35 U.S.C. § 102(a)(1) is affirmed.
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The Examiner’s rejections of claims 8, 10, 12, and 18 as being
unpatentable under 35 U.S.C. § 103 are affirmed.
DECISION SUMMARY
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–7, 9, 11,
13–17, 19,
20
102(a)(1) Youm 1–7, 9, 11,
13–17, 19,
20

8 103 Youm, Cho, Giordano 8
12, 18 103 Youm, Cho,
Kwidzinski
12, 18
10 103 Youm, Cho, Anderson 10
Overall
Outcome

1–20
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED