Imagination Technologies Limited

Patent Trials and Appeals Board

Feb 2, 2022

2020005849 (P.T.A.B. Feb. 2, 2022)

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/081,007 03/25/2016 Paul Murrin 8059-105939-01 5552 24197 7590 02/02/2022 KLARQUIST SPARKMAN, LLP 121 SW SALMON STREET SUITE 1600 PORTLAND, OR 97204 EXAMINER GIROUX, GEORGE ART UNIT PAPER NUMBER 2128 NOTIFICATION DATE DELIVERY MODE 02/02/2022 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docketing@klarquist.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte PAUL MURRIN, GARETH DAVIES, and ADRIAN J. ANDERSON ________________ Appeal 2020-005849 Application 15/081,007 Technology Center 2100 ____________ Before JAMES R. HUGHES, JOYCE CRAIG, and MATTHEW J. McNEILL, Administrative Patent Judges. McNEILL, Administrative Patent Judge. DECISION ON APPEAL Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1-12 and 14-20. Claim 13 is canceled. Appeal Br. 13 (Claims App.). We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42(a) (2012). Appellant identifies Imagination Technologies Limited as the real party in interest. Appeal Br. 1. Appeal 2020-005849 Application 15/081,007 2 STATEMENT OF THE CASE Introduction Appellant’s application relates to an “SIMD [Single Instruction Multiple Data] processing module compris[ing] multiple vector processing units, which can be used to execute an instruction on respective parts of a vector.” Spec. 5:28-30. Specifically, the application explains that “each of a plurality of vector processing units can execute an instruction on a respective part of a vector, whereby collectively the plurality of vector processing units cause the instruction to be executed on all of the data items of the vector.” Id. at 5:30-33. Claim 1 is illustrative of the appealed subject matter and reads as follows: 1. A SIMD processing module comprising: a plurality of vector processing units; and a control unit configured to: receive an instruction to be executed on a received vector; for each of said plurality of vector processing units, determine a respective vector position indication which indicates a different position of a respective part of the received vector on which a respective vector processing unit is to execute the same received instruction; and cause said plurality of vector processing units to execute, in parallel, the same received instruction on respective different parts of the received vector in accordance with the respective vector position indications, whereby collectively said plurality of vector processing units execute the received instruction on all of the parts of the received vector in parallel. Appeal 2020-005849 Application 15/081,007 3 The Examiner’s Rejection Claims 1-12 and 14-20 stand rejected under 35 U.S.C. § 103 as unpatentable over Gonion (US 2015/0058832 A1; Feb. 26, 2015) and Nickolls (US 2002/0087846 A1; July 4, 2002). Final Act. 3-12. ANALYSIS Appellant argues the Examiner errs in rejecting claim 1 because “Gonion discloses only a single vector execution unit 204” and Nickolls “does not describe parallel processing of multiple elements of a single vector as alleged.” See Appeal Br. 6, 8. In particular, Appellant argues that “Nickolls discloses executing multiple operations on multiple vectors in parallel, and does not anywhere teach parallel processing of multiple parts of a vector by the same received instruction.” Reply Br. 2-3. Appellant has not persuaded us of Examiner error. The Examiner finds Gonion teaches all the limitations of claim 1, except “it does not explicitly describe a plurality of vector processing units collectively performing vector processing on portions of the vector indicated by the position, in parallel.” See Final Act. 3-4. In particular, the Examiner finds “[t]he only teaching missing from Gonion is of a plurality of vector execution units performing the parallel execution.” Ans. 3-4. The Examiner notes, however, that “Gonion broadly mentions plural vector execution units in para. 0041.” Ans. 4. The Examiner finds Nickolls teaches the “plurality of vector processing units” recited in claim 1. Final Act. 4-5; Ans. 4. We find Nickolls at least suggests multiple vector processing units performing parallel processing of an instruction on the elements of a vector. Nickolls describes multiple data path execution units (see, e.g., Nickolls ¶ 136), and Appellant does not specifically argue that these data path Appeal 2020-005849 Application 15/081,007 4 execution units fail to teach the claimed “plurality of vector processing units.” See Appeal Br. Nickolls further describes that “[o]perations on multi- element vectors can be performed on multiple elements in parallel.” Nickolls ¶ 197. Appellant argues that this disclosure “relates to a plurality of multi- element vectors and describes that operations can be performed on multiple elements in parallel, but, importantly, it does not describe parallel processing of multiple elements of a single vector as alleged.” Appeal Br. 8. We agree with the Examiner that Appellant’s interpretation of Nickolls is incorrect. See Ans. 6. Where Nickolls describes performing parallel operations on “multiple elements in parallel” (Nickolls ¶ 197), one of ordinary skill in the art would most likely understand this to refer to multiple elements of the same vector. The background section of Nickolls identifies a limitation of conventional vector processors where they must “sequence vector processing element by element, one clock per element, resulting in many clock cycles to execute one vector instruction.” Id. ¶ 11. It follows that the detailed description in Nickolls would address this limitation with disclosure relating to parallel processing of multiple elements of a single vector, which is what we find in Nickolls’s paragraph 197. Appellant further argues the Examiner’s motivation to combine Nickolls with Gonion is unsupported. Appeal Br. 9. In particular, Appellant argues Nickolls actually raises “a problem associated with parallel instruction processing on different units.” Id. Appellant has not persuaded us of error in the Examiner’s motivation for combining the references. Nickolls teaches that avoiding delays in the context of vector processing could involve “complex ‘vector chaining’ controls to manage parallel instruction execution with different units.” Nickolls ¶ 11. But Nickolls also teaches that “[b]y invoking configurations Appeal 2020-005849 Application 15/081,007 5 that can utilize one or more execution units in parallel with the original instruction, parallel processing throughput and instruction density increase.” Id. ¶ 220. Thus, Nickolls describes an approach to parallel processing that has advantages, regardless of whether there are complexity concerns with certain prior art approaches. Appellant fails to persuasively identify a shortcoming in the Examiner’s combination of Nickolls with Gonion. Moreover, Gonion, in view of the creativity of on ordinarily skilled artisan, at least suggests using multiple vector processing units. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007) (“[A] court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.”). As the Examiner points out (Ans. 4), Gonion teaches that “processor 102 may include one or more mechanisms for vector processing (e.g., vector execution units)” (Gonion ¶ 41). In addition, the Examiner finds “that providing a plurality of vector execution units operating on the vector elements, as opposed to a single vector execution unit doing so in Gonion, amounts to a mere duplication of the essential working parts of the device.” Ans. 7. For these reasons, we sustain the obviousness rejection of claim 1. We also sustain the obviousness rejection of independent claims 18 and 20, as well as dependent claims 2-12 and 14-17, for which Appellant does not provide separate specific arguments. See Appeal Br. Appeal 2020-005849 Application 15/081,007 6 CONCLUSION In summary: Claims Rejected 35 U.S.C. § References Affirmed Reversed 1-12, 14-20 103 Gonion, Nickolls 1-12, 14-20 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2013). See 37 C.F.R. § 41.50(f) (2019). AFFIRMED