Imagination Technologies Limited

Patent Trials and Appeals Board

Dec 30, 2020

2019004686 (P.T.A.B. Dec. 30, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/856,393 09/16/2015 Theo Alan Drane 2645-0203US01 1434
125968 7590 12/30/2020
Potomac Law Group PLLC (IMGTEC)
8229 Boone Boulevard Suite 430
Vienna, VA 22182
EXAMINER
YAARY, MICHAEL D
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
12/30/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
Eofficeaction@appcoll.com
Patents@potomaclaw.com
vdeluca@potomaclaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte THEO ALAN DRANE
____________

Appeal 2019-004686
Application 14/856,3931
Technology Center 2100
____________

Before ELENI MANTIS MERCADER, NORMAN H. BEAMER, and
GARTH D. BAER, Administrative Patent Judges.

BEAMER, Administrative Patent Judge.

DECISION ON APPEAL
Appellant appeals under 35 U.S.C. § 134(a) from the Examiner’s non-
final rejection of claims 1–19. We have jurisdiction over the pending
rejected claims under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies Imagination Technologies Limited as
the real party in interest. (Appeal Br. 1.)
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THE INVENTION
Appellant’s disclosed and claimed invention is directed to
“implementing fixed-point polynomials in hardware logic.” (Spec. ¶ 8.)
Independent claim 1, reproduced below, is illustrative of the subject
matter on appeal:
1. A method of generating an implementation of a fixed-
point polynomial with rational coefficients in hardware logic
that satisfies a defined error bound, the method comprising:
receiving, in a synthesizer module, the polynomial as a
data-flow graph comprising one or more nodes, wherein each
node is either a sum-of-products operator or a constant division
operator;
computing, in the synthesizer module, an error bound for
each node in the dataflow graph based on the defined error
bound for the polynomial;
optimizing, in the synthesizer module, a single
summation array for each node using a truncation scheme and
the error bound for each node;
calculating, in the synthesizer module, an updated error
bound for each node in the data-flow graph, wherein the
calculating of updated error bounds redistributes error bounds
between nodes to allow for synthesis of the fixed-point
polynomial with a reduced physical size whilst satisfying the
defined error bound; and
further optimizing, in the synthesizer module, the single
summation array for each node using the truncation scheme and
the updated error bound for the node; and
generating the implementation of the fixed-point
polynomial in hardware logic using the optimized single
summation arrays.
(Appeal Br. 10 (Claims Appendix).)
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REJECTIONS
The Examiner rejected claims 1–19 “under 35 U.S.C. § 101 as being
directed to non-statutory subject matter.” (Non-Final Act. 4.2)
ISSUE ON APPEAL
Appellant’s arguments in the Appeal and Reply Briefs present the
following issue:3
Whether the Examiner erred in finding claims 1–19 as directed to
non-statutory subject matter. (Appeal Br. 6–9; Reply Br. 1–6.)

ANALYSIS
We have reviewed the Examiner’s rejections in light of Appellant’s
arguments. Arguments Appellant could have made but chose not to make
are deemed to be waived. See 37 C.F.R. § 41.37(c)(1)(iv).
The Examiner determines the claims are patent ineligible under
35 U.S.C. § 101, because
under the broadest reasonable interpretation, these limitations are
directed [to] mathematical concepts as in mathematical
calculations. This is emphasized in the specification as seen in
drawing 10. Drawing 10 diagrams the method of operation of the

2 The Examiner’s Answer issued new grounds of rejection for claims 1–19
under 35 U.S.C. § 101, in view of the 2019 Revised Patent Subject Matter
Eligibility Guidance. (Ans. 3; see 84 Fed. Reg. 50 (Jan. 7, 2019)
(hereinafter “Revised Guidance”).)
3 Rather than reiterate the arguments of Appellant and the positions of the
Examiner, we refer to the Appeal Brief (filed Oct. 29, 2018); the Reply Brief
(filed May 29, 2019); the Non-Final Office Action (mailed May 25, 2018);
and the Examiner’s Answer (mailed Mar. 29, 2019) for the respective
details.
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steps in which the mathematical calculations of claim 1 are
performed.
(Ans. 5; see also Alice Corp. Pty. Ltd. v. CLS Bank Int’l, 573 U.S. 208, 217
(2014) (Describing the two-step framework “for distinguishing patents that
claim laws of nature, natural phenomena, and abstract ideas from those that
claim patent-eligible applications of those concepts.”).)
The Examiner further finds that with respect to claim 1, “the
computing, optimizing, and calculating is done in a ‘synthesizer module’
[and] is nothing more than a form of ‘apply it’ or equivalent.” (Ans. 5, citing
MPEP § 2106.05(f).) The Examiner concludes that the additional claim
limitations do not amount to significantly more, because “the generating step
does not amount to anything more than what is well-understood, routine, and
conventional activity.” (Ans. 6, citing Ercegovac, “A General Hardware-
Oriented Method for Evaluation of Functions and Computations in a Digital
Computer,” IEEE Transactions on Computers, Vol. C-26, No. 7, pp. 667–
680 (July, 1997).)
Appellant argues that the “application of Prong 1 of the [Revised
Guidance] to claim 1 shows that the claim does not recite any ‘abstract idea’
and thus the analysis should be concluded.” (Reply Br. 4.) Appellant
contends that “the Answer has failed to properly analyze the claim as a
whole to determine what the inventor has invented and seeks to patent”
(Reply Br. 4) and that claim 1 “is clearly directed to a patent-eligible method
of generating a hardware logic implementation for a fixed-point polynomial
that satisfies a defined error bound.” (Reply Br. 5 (emphasis omitted).)
An invention is patent-eligible if it claims a “new and useful process,
machine, manufacture, or composition of matter.” 35 U.S.C. § 101. Here,
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independent claim 1 and its dependent claims relate to a method, and
independent claims 17 and 18 and dependent claim 19 relate to an apparatus
— i.e., a process and machine, respectively. However, the Supreme Court
has long held that “[l]aws of nature, natural phenomena, and abstract ideas
are not patentable.” Alice, 573 U.S. at 216 (quoting Assoc. for Molecular
Pathology v. Myriad Genetics, Inc., 569 U.S. 576, 589–90 (2013)). The
“abstract ideas” category embodies the longstanding rule that an idea, by
itself, is not patentable. Alice, 573 U.S. at 216–17.
In Alice, the Supreme Court sets forth an analytical “framework for
distinguishing patents that claim laws of nature, natural phenomena, and
abstract ideas from those that claim patent-eligible applications of those
concepts.” Id. at 217. The first step in the analysis is to “determine whether
the claims at issue are directed to one of those patent-ineligible concepts,”
such as an abstract idea. Id. Concepts determined to be abstract ideas, and
thus patent ineligible, include certain methods of organizing human activity
such as fundamental economic practices (Alice, 573 U.S. at 219–20; see also
Bilski v. Kappos, 561 U.S. 593, 611 (2010)); mathematical concepts (Parker
v. Flook, 437 U.S. 584, 594–95 (1978)); and mental processes (Gottschalk v.
Benson, 409 U.S. 63, 69 (1972)). Concepts determined to be patent eligible
include physical and chemical processes, such as “molding rubber products”
(Diamond v. Diehr, 450 U.S. 175, 191 (1981)); “tanning, dyeing, making
water-proof cloth, vulcanizing India rubber, smelting ores” (id. at 182 n.7
(quoting Corning v. Burden, 56 U.S. 252, 267–68 (1853))); and
“manufacturing flour” (Benson, 409 U.S. at 69 (citing Cochrane v. Deener,
94 U.S. 780, 785 (1876))).
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If the claims are directed to a patent-ineligible concept, the second
step in the Alice/Mayo analysis is to consider the elements of the claims
“individually and ‘as an ordered combination’” to determine whether there
are additional elements that “‘transform the nature of the claim’ into a
patent-eligible application.” Alice, 573 U.S. at 217 (quoting Mayo
Collaborative Servs. v. Prometheus Labs., Inc., 566 U.S. 66, 78–79 (2012)).
In other words, the second step is to “search for an ‘inventive concept’ —
i.e., an element or combination of elements that is ‘sufficient to ensure that
the patent in practice amounts to significantly more than a patent upon the
[ineligible concept] itself.’” Alice, 573 U.S. at 217–18 (quoting Mayo, 566
U.S. at 72–73) (alteration in original). “A claim that recites an abstract idea
must include ‘additional features’ to ensure ‘that the [claim] is more than a
drafting effort designed to monopolize the [abstract idea].’” Alice, 573 U.S.
at 221. A “transformation into a patent-eligible application requires ‘more
than simply stat[ing] the [abstract idea] while adding the words “apply it.”’”
Id.
Further to the Alice/Mayo analytical framework, and acknowledged
by Appellant in the Briefs, the USPTO published the Revised Guidance on
the application of § 101. See also USPTO October 2019 Update: Subject
Matter Eligibility (Oct. 17, 2019) (hereinafter “Update”), noticed at 84 Fed.
Reg. 55942 (Oct. 18, 2019). Under the Revised Guidance, the Office first
looks to whether the claim recites:
(1) any judicial exceptions, including certain groupings of abstract
ideas (i.e., mathematical concepts, certain methods of organizing
human interactions such as a fundamental economic practice, or
mental processes); and
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(2) additional elements that integrate the judicial exception into a
practical application (see MPEP § 2106.05(a)–(c), (e)–(h)).
Only if a claim (1) recites a judicial exception and (2) does not integrate that
exception into a practical application, does the Office then look to whether
the claim:
(3) adds a specific limitation beyond the judicial exception that are not
“well-understood, routine, conventional” in the field (see MPEP
§ 2106.05(d)); or
(4) simply appends well-understood, routine, conventional activities
previously known to the industry, specified at a high level of
generality, to the judicial exception.
See Revised Guidance.
In evaluating the claims at issue, we consider claim 1 as
representative, consistent with how Appellant and the Examiner analyze the
claims. See 37 C.F.R. § 41.37(c)(1)(iv)(2016). Omitting the portions of the
claim invoking use of generic technology, the remaining limitations of claim
1 elaborate on a method of generating an implementation of a fixed-point
polynomial with rational coefficients in hardware logic, via the steps of:
(a) receiving a polynomial as a data-flow graph;
(b) computing an error bound;
(c) optimizing a single summation array;
(d) calculating an updated error bound;
(e) further optimizing the single summation array; and
(f) generating the implementation of the fixed-point polynomial.
We agree with the Examiner that Appellant’s Figure 10 “diagrams the
method of operation of the steps in which the mathematical calculations of
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claim 1 are performed” (Ans. 5), and apart from the use of generic
technology, these limitations describe steps relying on mathematical
calculations whose aim is to “distribute the user defined maximum absolute
error (which may also be referred to as the allowable error) between the
operators in a data-flow graph (DFG) which represents the polynomial”
while “guaranteeing that the user defined maximum absolute error is not
exceeded.” (Spec. ¶ 32; see also Spec. ¶¶ 76–82.) These limitations
comprise mathematical relationships, mathematical formulas or equations, or
mathematical calculations; thus, the claim recites the abstract idea of
“[m]athematical concepts.” (Revised Guidance, 84 Fed. Reg. at 52.)
Therefore, we agree with the Examiner that the subject matter of
claim 1 recites an abstract idea, as do the remaining claims.
Further pursuant to the Revised Guidance, we consider whether there
are additional elements set forth in claim 1 that integrate the judicial
exception into a practical application. (Revised Guidance, 84 Fed. Reg. at
54–55.) Here, the “calculating” step includes that “the calculating of
updated error bounds redistributes error bounds between nodes to allow for
synthesis of the fixed-point polynomial with a reduced physical size whilst
satisfying the defined error bound” and claim 1 culminates in “generating
the implementation of the fixed-point polynomial in hardware logic using
the optimized single summation arrays.”
When these additional elements are considered, the claimed invention
resembles the claimed subject matter in Diehr, regarding “a process for
curing synthetic rubber which includes in several of its steps the use of a
mathematical formula and a programmed digital computer.” Diehr, 450
U.S. 175 at 177. In that case the Supreme Court said
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when a claim containing a mathematical formula implements or
applies that formula in a structure or process which, when
considered as a whole, is performing a function which the patent
laws were designed to protect (e.g., transforming or reducing an
article to a different state or thing), then the claim satisfies the
requirements of § 101.

Diehr, 450 U.S. at 192–93. Here, the ultimate aim of claim 1 is to
“generat[e] the implementation of the fixed-point polynomial in hardware
logic” such that the resulting fixed-point polynomial has “a reduced physical
size whilst satisfying the defined error bound.”
This is significantly more than the recitation of the abstract idea of
mathematical concepts; the disclosure explains the benefits of generating the
polynomial in hardware logic as
aid[ing] miniaturization of components and the devices (e.g.
smartphones, tablet computers and other computing devices) in
which the components are used. In addition, or instead, it
enables more functionality to be implemented within a similar
area of silicon chip. By reducing the physical size (i.e. area) that
is used, more ICs can be fabricated from a single silicon wafer,
which reduces the overall cost per die.

(Spec. ¶ 83.) The fact that polynomial hardware level implementation has
been performed since at least 1977 (the publication date of Ercegovac) does
not negate the particular benefits disclosed and claimed, which is a strong
indication that the claim as whole does more that well understood, routine,
and conventional activity.
In other words, “the claim as a whole integrates the recited judicial
exception into a practical application of the exception.” (Revised Guidance,
84 Fed. Reg. at 54.)
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Accordingly, we reverse the Examiner’s patent-eligibility rejection of
independent claim 1, and independent claims 17 and 18 commensurate in
scope, and all dependent claims.

CONCLUSION SUMMARY
In summary:

Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1–19 101 Patent Eligibility 1–19

REVERSED