Imagination Technologies, Limited

Patent Trials and Appeals Board

Dec 16, 2020

2019004009 (P.T.A.B. Dec. 16, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/516,643 10/17/2014 Leonard Rarick 2645-0168US01 5792
104840 7590 12/16/2020
Imagination Technologies
c/o Potomac Law Group PLLC
8229 Boone Boulevard Suite 430
Vienna, VA 22182
EXAMINER
LAROCQUE, EMILY E
ART UNIT PAPER NUMBER
2182
NOTIFICATION DATE DELIVERY MODE
12/16/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
Eofficeaction@appcoll.com
Patents@potomaclaw.com
vdeluca@potomaclaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte LEONARD RARICK
____________________

Appeal 2019-004009
Application 14/516,643
Technology Center 2100
____________________

Before BARBARA A. PARVIS, JAMES W. DEJMEK, and
MICHAEL T. CYGAN, Administrative Patent Judges.

DEJMEK, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1, 3–7, and 14–19. Appellant has cancelled or withdrawn from
consideration claims 2 and 8–13. Appeal Br. 2. We have jurisdiction over
the remaining pending claims under 35 U.S.C. § 6(b).
We reverse.

1 Throughout this Decision, we use the word “Appellant” to refer to
“applicant” as defined in 37 C.F.R. § 1.42 (2018). Appellant identifies
Imagination Technologies, Limited as the real party in interest. Appeal
Br. 2.
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Application 14/516,643

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STATEMENT OF THE CASE
Introduction
Appellant’s disclosed and claimed invention generally relates to
“microprocessor microarchitecture . . . [related to] implementations of divide
and square root functions in hardware.” Spec. ¶ 1. According to the
Specification, floating point multiplier circuits consume a relatively large
area of semiconductor substrate and increase the cost of a processor. Spec.
¶ 2. For processors without separate circuitry for floating point
multiplication, an emulation mode, which operates “much slower than a
dedicated hardware floating point unit,” is performed in microcode. Spec.
¶ 2.
In a disclosed embodiment, a processor comprising an arrangement of
a full-precision multiplier and a small, limited-precision multiplier is used to
perform divide and square root operations by using a look-up table (LUT) as
an initial approximation of a reciprocal of a denominator (in a divide
operation) as an input to a limited-precision multiplier. See Spec. ¶¶ 8–10,
19, 23–28. After a desired number of iterations, the obtained value (e.g., the
reciprocal) is multiplied with the numerator using the full-precision
multiplier. Spec. ¶¶ 25–28. According to the Specification, the arrangement
of the LUT, small multiplier, and full-precision multiplier “is designed to
produce a result accurate to within required precision within a pre-
determined number of iterations.” Spec. ¶ 30.
Claim 1 is representative of the subject matter on appeal and is
reproduced below:
1. An apparatus for performing an iterative arithmetic
operation on an input value to obtain an output value that is used
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to execute an instruction requesting an arithmetic operation on
an operand by said input value, comprising:
initial approximation circuitry configured to provide, from
at least a portion of said input value, an initial approximation of
said output value, the initial approximation of the output value
having a second number of bits of precision that is less than a
first number of bits of precision to which said output value is to
be produced;
limited precision multiplier circuitry configured to receive
the initial approximation and multiply the initial approximation
with another value to obtain a first multiplication result;
full-precision multiplier circuitry coupled to receive the
first multiplication result from the limited precision multiplier
circuitry and configured to multiply the first multiplication result
from the limited precision multiplier circuitry with another value
to obtain a second multiplication result on which said output
value is based, the second multiplication result having no fewer
than the first number of bits of precision, wherein the full-
precision multiplier circuitry requires a first number of clock
cycles to finish its multiplication, and a combined number of
clock cycles required by the initial approximation circuitry to
provide the initial approximation and the limited precision
multiplier circuitry to complete a multiplication is equal to or less
than the first number of clock cycles; and
an output configured to output said output value.

The Examiner’s Rejection
Claims 1, 3–7, and 14–19 stand rejected under 35 U.S.C. § 101 as
being directed to patent-ineligible subject matter. Final Act. 10–12.

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ANALYSIS2
Appellant disputes the Examiner’s conclusion that the pending claims
are directed to patent-ineligible subject matter. Appeal Br. 6–13; Reply
Br. 1–5. In particular, Appellant argues the Examiner mischaracterizes the
claims as merely being directed to a mathematical concept rather than being
directed to “a specific and unique combination of structure.” Appeal Br. 6–
9, 12–13 (asserting the claimed invention “provide[s] a processor with the
ability to perform required floating point operations, without microcode
emulation and without a dedicated floating point unit.”). Additionally,
Appellant argues the focus of the claims is on “an improvement of the
operation of a processor itself, or in other words to an improvement in
technology.” Appeal Br. 7–9; Reply Br. 3–4. Moreover, Appellant argues
the Examiner “fails to provide any factual evidence that the claimed
combination of elements in claims 1 and 14 was ‘well-understood, routine,
and conventional’ . . . .” Appeal Br. 10.
The Supreme Court’s two-step framework guides our analysis of
patent eligibility under 35 U.S.C. § 101. Alice Corp. v. CLS Bank Int’l, 573
U.S. 208, 217 (2014). In addition, the Office has published revised guidance
for evaluating subject matter eligibility under 35 U.S.C. § 101, specifically
with respect to applying the Alice framework. USPTO, 2019 Revised Patent
Subject Matter Eligibility Guidance, 84 Fed. Reg. 50 (Jan. 7, 2019) (“Office

2 Throughout this Decision, we have considered the Appeal Brief, filed
November 5, 2018 (“Appeal Br.”); the Reply Brief, filed April 26, 2019
(“Reply Br.”); the Examiner’s Answer, mailed February 26, 2019 (“Ans.”);
and the Final Office Action, mailed May 3, 2018 (“Final Act.”), from which
this Appeal is taken.
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Guidance”).3 If a claim falls within one of the statutory categories of patent
eligibility (i.e., a process, machine, manufacture, or composition of matter)
then the first inquiry is whether the claim is directed to one of the judicially
recognized exceptions (i.e., a law of nature, a natural phenomenon, or an
abstract idea). Alice, 573 U.S. at 217. As part of this inquiry, we must “look
at the ‘focus of the claimed advance over the prior art’ to determine if the
claim’s ‘character as a whole’ is directed to excluded subject matter.”
Affinity Labs of Tex., LLC v. DIRECTV, LLC, 838 F.3d 1253, 1257–58 (Fed.
Cir. 2016). Per the Office Guidance, this first inquiry (“Step 2A”) has two
prongs of analysis: (i) does the claim set forth or describe a judicial
exception (e.g., an abstract idea such as a mental process), and (ii) if so, is
the judicial exception integrated into a practical application. Office
Guidance, 84 Fed. Reg. at 54; see also MPEP § 2106.04(II)(A). Under the
Office Guidance, if the judicial exception is integrated into a practical
application, see infra, the claim is patent eligible under § 101. Office
Guidance, 84 Fed. Reg. at 54–55; see also MPEP § 2106.04(d). If the claim
is directed to a judicial exception (i.e., recites a judicial exception and does
not integrate the exception into a practical application), the next step (“Step
2B”) is to determine whether any element, or combination of elements,
amounts to significantly more than the judicial exception. Alice, 573 U.S. at
217; Office Guidance, 84 Fed. Reg. at 56; see also MPEP § 2106.05.
In rejecting the pending claims under 35 U.S.C. § 101, the Examiner
concludes the claims are directed to iterative arithmetic operations. Final

3 The Office Guidance, as well as guidance set forth in the Berkheimer
Memorandum, have been incorporated into the latest revision of the Manual
of Patent Examination Procedure (“MPEP”) §§ 2103–2106.07(c) (9th ed.,
Rev. 10.2019, June 2020).
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Act. 10–11; Ans. 4 (determining the claims are “directed to the abstract idea
of mathematical relationships and formulas without significantly more”). In
addition, the Examiner determines the combination of initial approximation
circuitry, limited precision multiplier circuitry, and full-precision multiplier
circuity (i.e., additional elements to the identified abstract idea elements)
does not result in a technological improvement. Ans. 6. Rather, the
Examiner determines that any improvement merely flows from the particular
mathematical algorithm being performed. Ans. 6–7. Further, the Examiner
finds “the additional elements, taken individually, use conventional
multipliers, . . . [and when] [c]onsidered as an ordered combination, the
combination merely flows as a natural consequence of the mathematical
steps.” Ans. 8.
Although we agree with the Examiner that the claims involve
mathematical calculations (i.e., performing an iterative arithmetic operation
and multiplication operations), we are mindful that “an invention is not
rendered ineligible for patent simply because it involves an abstract
concept.” Alice, 573 U.S. at 217. However, unlike withdrawn claim 8,
where, arguably, the focus of the claim was merely on a method for
performing a mathematical operation, we conclude the focus of independent
claims 1 and 14 is on the performance of an iterative arithmetic operation by
means of a particular arrangement of components (i.e., a particular
machine).
Claim 1 is reproduced below and includes those limitations identified
by the Examiner (see Ans. 4–5) as reciting the abstract idea of mathematical
relationships and formulas emphasized in italics:
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1. An apparatus for performing an iterative arithmetic
operation on an input value to obtain an output value that is used
to execute an instruction requesting an arithmetic operation on
an operand by said input value, comprising:
initial approximation circuitry configured to provide, from
at least a portion of said input value, an initial approximation of
said output value, the initial approximation of the output value
having a second number of bits of precision that is less than a
first number of bits of precision to which said output value is to
be produced;
limited precision multiplier circuitry configured to receive
the initial approximation and multiply the initial approximation
with another value to obtain a first multiplication result;
full-precision multiplier circuitry coupled to receive the
first multiplication result from the limited precision multiplier
circuitry and configured to multiply the first multiplication result
from the limited precision multiplier circuitry with another value
to obtain a second multiplication result on which said output
value is based, the second multiplication result having no fewer
than the first number of bits of precision, wherein the full-
precision multiplier circuitry requires a first number of clock
cycles to finish its multiplication, and a combined number of
clock cycles required by the initial approximation circuitry to
provide the initial approximation and the limited precision
multiplier circuitry to complete a multiplication is equal to or less
than the first number of clock cycles; and
an output configured to output said output value.
Because the claim recites a judicial exception (i.e., a mathematical
concept), we next determine whether the claim integrates the judicial
exception into a practical application. Office Guidance, 84 Fed. Reg. at 54;
see also MPEP § 2106.04(d). To determine whether the judicial exception is
integrated into a practical application, we identify whether there are “any
additional elements recited in the claim beyond the judicial exception(s)”
and evaluate those elements to determine whether they integrate the judicial
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exception into a recognized practical application. Office Guidance, 84 Fed.
Reg. at 54–55 (emphasis added); see also MPEP § 2106.05(a)–(c), (e)–(h).
Appellant argues that the combination and arrangement recited in
claim 1 is specific and unique and integrates the judicial exception into a
practical application. Appeal Br. 9; Reply Br. 4.
We consider whether an element or combination of elements is a
particular machine. See MPEP § 2106.05(b) (emphasis added). Contrary to
the Examiner, we find the additional limitations (i.e., an apparatus
comprising (i) initial approximation circuitry; (ii) limited precision
multiplier circuitry; and (iii) full-precision multiplier circuitry), when
considered as an ordered combination, integrate the judicial exception into a
practical application. As opposed to merely performing the arithmetic
operations on a generic computing processor, the claims recite a particular
structure of the additional elements—i.e., a limited precision multiplier
circuit that receives an initial approximation of an output value (based on an
input value) from initial approximation circuitry and multiplies the received
value with another value, and a full-precision multiplier circuit that receives
the output from the limited precision multiplier circuitry and multiplies the
received value with another value to obtain a second multiplication result—
that perform their designated functions within recited timing constraints (i.e.,
“wherein the full-precision multiplier circuitry requires a first number of
clock cycles to finish its multiplication, and a combined number of clock
cycles required by the initial approximation circuitry to provide the initial
approximation and the limited precision multiplier circuitry to complete a
multiplication is equal to or less than the first number of clock cycles”). See
claim 1. Consistent with the Specification, we do not find the claimed
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structure to be a generic processor on which the abstract idea (mathematical
concept) is performed, but rather a “particular machine” to apply or to use
the judicial exception (see MPEP § 2106.05(b)). See also Mackay Radio &
Tel. Co. v. Radio Corp. of Am., 306 U.S. 86, 94 (1939) (explaining that
although “a scientific truth, or the mathematical expression of it, is not
patentable invention, a novel and useful structure created with the aid of
knowledge of scientific truth may be”).
Because we conclude the additional elements integrate the abstract
idea of performing an iterative arithmetic operation on an input value to
obtain an output value into a practical application, the claims are patent
eligible.
Moreover, as set forth in our Office Guidance, at Step 2B, the
Examiner “should continue to consider” whether any identified additional
elements or combination of elements adds a specific limitation or
combination of limitations that are not well-understood, routine,
conventional activity in the field, or simply appends well-understood,
routine, conventional activities previously known to the industry specified at
a high level of generality. See Office Guidance, 84 Fed. Reg. at 56; see also
MPEP § 2106.05(II). “Whether something is well-understood, routine, and
conventional to a skilled artisan at the time of the patent is a factual
determination.” Berkheimer v. HP Inc., 881 F.3d 1360, 1369 (Fed. Cir.
2018).
We find the court’s holding in BASCOM instructive.4 In BASCOM,
the court determined that although filtering Internet content is a

4 BASCOM Glob. Internet Servs., Inc. v. AT&T Mobility LLC, 827 F.3d 1341
(Fed. Cir. 2016).
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“longstanding, well-known method of organizing human behavior, similar to
concepts previously found to be abstract,” the inventors had recognized “a
filter implementation versatile enough that it could be adapted to many
different users’ preferences while also installed remotely in a single
location.” BASCOM, 827 F.3d at 1348–51. Thus, when considered as an
ordered combination, the court concluded the claims provided “an inventive
concept can be found in the non-conventional and non-generic arrangement
of known, conventional pieces.” BASCOM, 827 F.3d at 1350.
The court’s reasoning in BASCOM is applicable here. To the extent
that the Examiner characterizes the individual elements—i.e., initial
approximation circuitry, limited precision multiplier, and full-precision
multiplier—as being conventional (see Final Act. 12 (findings the identified
elements as “merely hardware elements”); see also Ans. 6 (describing the
elements as “configured in hardware”), 8 (finding the claimed invention uses
“conventional multipliers”); Spec. ¶¶ 23–28, Fig.1), as discussed above, it is
the ordered combination of these that is unconventional. We do not find the
Examiner’s statement that the ordered combination of the additional
elements “merely flows as a natural consequence of the mathematical steps
of the Newton-Raphson [(i.e., mathematical)] algorithm” (see Ans. 8) is
supported with the requisite evidence consistent with the Berkheimer
Memorandum. Accordingly, when considered as an ordered combination,
we conclude the pending claims provide an inventive concept by the
unconventional arrangement of generic components to yield a technological
improvement.
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For the reasons discussed supra, we are persuaded of Examiner error.
Accordingly, we do not sustain the Examiner’s rejection under 35 U.S.C.
§ 101 of claims 1, 3–7, and 14–19.

CONCLUSION
We reverse the Examiner’s decision rejecting claims 1, 3–7, and 14–
19 under 35 U.S.C. § 101.

DECISION SUMMARY
Claims
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
1, 3–7, 14–
19
101 Eligibility 1, 3–7,
14–19

REVERSED