HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Patent Trials and Appeals Board

Dec 9, 2020

2019004622 (P.T.A.B. Dec. 9, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/224,988 08/01/2016 Gregg B. Lesartre 90222250 6758
56436 7590 12/09/2020
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
EXAMINER
PATEL, KAMINI B
ART UNIT PAPER NUMBER
2114
NOTIFICATION DATE DELIVERY MODE
12/09/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
chris.mania@hpe.com
hpe.ip.mail@hpe.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte GREGG B. LESARTRE and MARTIN FOLTIN
____________________

Appeal 2019-004622
Application 15/224,988
Technology Center 2100
____________________

Before JOSEPH L. DIXON, DAVID M. KOHUT, and
JON M. JURGOVAN, Administrative Patent Judges.

DIXON, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Appellant1 appeals under 35 U.S.C. § 134(a) from a final rejection of
claims 1–15. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.

The claims are directed to a device and method for adjusting
parameters of a memory having a plurality of dies, the adjustment performed
by logic that “determine[s] a tolerable bit error rate (BER) of the memory
based on whether one of the plurality of dies has failed, and adjust[s] a

1 We use the word “Appellant” to refer to “applicant(s)” as defined in
37 C.F.R. § 1.42. The real party in interest is Hewlett Packard Enterprise
Development LP. (Appeal Br. 1.)
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Application 15/224,988

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parameter of the memory based on the tolerable BER.” (Spec. Title;
Abstract.)
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A method comprising:
determining a tolerable bit error rate (BER) of a memory
based on whether a die of the memory has failed, the tolerable
BER indicating a threshold under which the memory is to
operate;
responsive to determining the tolerable BER, adjusting a
parameter of the memory based on the tolerable BER, the
memory correspondingly operating at a BER under the
tolerable BER.
(Appeal Br. 10 (Claims Appendix).)

REFERENCES
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Brittain et al. US 2008/0072116 A1 Mar. 20, 2008
(“Brittain”)

Schuette et al. US 2011/0173484 A1 July 14, 2011
(“Schuette”)

Chung et al. US 2013/0024735 A1 Jan. 24, 2013
(“Chung”)

Patapoutian et al. US 2013/0094288 A1 Apr. 18, 2013
(“Patapoutian”)

Sood et al. US 8,477,549 B1 July 2, 2013
(“Sood”)
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Application 15/224,988

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REJECTIONS2
The Examiner made the following rejections:
Claims 1, 2, 6–9, and 12–15 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Schuette in view of Chung and Patapoutian.3 (Final
Act. 4–8.)
Claims 3, 4, and 10 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Schuette in view of Chung and Patapoutian, and further in
view of Brittain. (Final Act. 8–9.)
Claims 5 and 11 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Schuette in view of Chung and Patapoutian, and further in
view of Sood. (Final Act. 9–10.)

ANALYSIS
With respect to independent claim 1, the Examiner finds Schuette’s
“integrity checks of the wear indicator means and monitoring a bit error rate
thereof” teaches the claimed “determining a tolerable bit error rate (BER) of
a memory based on whether a die of the memory has failed.” (Final Act. 4
(citing Schuette ¶¶ 12, 25, Fig. 2); Ans. 12.) The Examiner acknowledges
“Schutte[sic] does not specifically disclose[] the tolerable BER indicating a

2 Claims 1–15 were rejected under 35 U.S.C. § 112(a) as failing to comply
with the written description requirement. (Final Act. 2–3.) However, this
rejection was withdrawn in the Examiner’s Answer and is no longer pending
on appeal. (Ans. 11–12.)
3 The Examiner’s statement of the rejection in the Final Action contains a
typo—it omits Schuette from the listing of references used in the rejection.
(See Final Act. 4.) Schuette is used in the rejection of claims 1, 2, 6–9, and
12–15, as shown by the detailed description of the rejection (see Final Act.
4–5). The Examiner’s Answer acknowledges the typo (see Ans. 12).
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4
threshold under which the memory is to operate” but asserts Chung teaches
this limitation. (Final Act. 4–5 (citing Chung ¶ 16) (emphasis removed).)
The Examiner reasons Schuette and Chung are combinable to determine a
tolerable BER threshold as recited in claim 1. (See Final Act. 5.) We do not
agree.
We agree with Appellant that Schuette and Chung, alone or in
combination, fail to teach or suggest determining a tolerable BER threshold
of a memory based on whether a memory die has failed, as recited in claim
1. (Appeal Br. 6–8; Reply Br. 1–3.) As Appellant explains, Schuette merely
measures and monitors an actual BER of particular memory test blocks
(wear-indicator blocks 26), and if that BER is too high, Schuette implements
corrective actions, such as warning of potential memory failures and
initiating backup or data erasure. (Appeal Br. 6 (citing Schuette ¶¶ 12, 25);
Reply Br. 1–2; see Schuette ¶¶ 12–14, 17, and 25.) Thus, Schuette
determines “whether the actual BER is too high, and if so, performs actions
so that data is not lost or is not compromised” but “does not determine any
BER (actual or otherwise), based on whether a die of the memory has
failed.” (Appeal Br. 6–7.)
The Examiner responds that the claimed “whether a die of memory
has failed” is taught by Schuette’s “comparing the checksum to the
subsequent reads of checksums of the same data range [that] identifies the
failure.” (Ans. 12.) We disagree. Schuette’s checksum comparison is used
to monitor an actual BER of memory test blocks “to predict failures of the
data blocks [] before they occur,” but the checksums are not used to
determine a tolerable BER based on whether a memory die has failed. (See
Schuette ¶ 25 (emphasis added).)
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Chung does not make up for the above-noted deficiencies of Schuette,
as Chung does not teach or suggest the claimed “determining” either.
(Appeal Br. 7–8; Reply Br. 1–2.) As Appellant explains, Chung sets a
threshold for a tolerable BER to “one-half of the maximum correctable bit
error rate of the ECC implementation used” but
Chung . . . does not teach that the tolerable BER is set based on
[] whether a die of the memory has failed, as recited in the claim
language. Rather, the tolerable BER is set based on the specific
ECC implementation that is used, such as one-half of the
maximum correctable bit error rate of the ECC implementation
that is being used. . . . The ECC implementation that is used, in
other words, speaks to how robust the memory in question is to
memory failures, and does not indicate whether a die of the
memory has actually failed. That a given memory uses a
particular ECC implementation does not indicate whether any
die of the memory has failed or not.

(Appeal Br. 7 (citing Chung ¶¶ 7–8, 16).)
The Examiner’s rejection has also failed to provide an adequate
reason based on rational underpinnings explaining why the combination of
Schuette and Chung would determine a tolerable BER threshold as claimed.
As discussed supra, neither Schuette nor Chung teaches or suggests
determining a tolerable BER based on whether a memory die has failed.
Furthermore, the Examiner’s response in the Answer (“examiner believes
Chung discloses the tolerable BER indicating a threshold under which the
memory is to operate,” see Ans. 13) does not address Appellant’s arguments
regarding the deficiencies of Chung.
The Examiner does not use the additional teachings of Patapoutian,
Brittain, and Sood to cure the above-noted deficiencies of Schuette and
Chung. As the Examiner has not shown where the references teach
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determining a tolerable BER threshold based on whether a die of the
memory has failed (as recited in claim 1, and similarly in claims 8 and 14),
we do not sustain the Examiner’s § 103 rejections of independent claims 1,
8, and 14, and claims 2–7, 9–13, and 15 dependent therefrom.4

CONCLUSION
The Examiner erred in rejecting claims 1–15 based upon obviousness.

DECISION
For the above reasons, we REVERSE the Examiner’s obviousness
rejections of claims 1–15 under 35 U.S.C. § 103.

In summary:
Claims
Rejected
35 U.S.C.§ Basis Affirmed Reversed
1, 2, 6–9, 12–15 103 Schuette, Chung,
Patapoutian
1, 2, 6–9,
12–15
3, 4, 10 103 Schuette, Chung,
Patapoutian,
Brittain
3, 4, 10
5, 11 103 Schuette, Chung,
Patapoutian, Sood
5, 11
Overall Outcome 1–15

4 While the Examiner’s current findings do not support affirmance of the
rejections, in the event of any further prosecution, the Examiner may want to
re-review Patapoutian in more detail to assess whether Patapoutian reads on
the claimed “determining.” See, e.g., Patapoutian ¶¶ 1, 16, 22, 28, 49, 50,
52.
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REVERSED