HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Patent Trials and Appeals Board

Jan 14, 2021

2019004507 (P.T.A.B. Jan. 14, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/518,218 04/10/2017 Gregg B. LESARTRE 90402189 6736
56436 7590 01/14/2021
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
EXAMINER
ZAMAN, FAISAL M
ART UNIT PAPER NUMBER
2185
NOTIFICATION DATE DELIVERY MODE
01/14/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
chris.mania@hpe.com
hpe.ip.mail@hpe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GREGG B. LESARTRE, JOSEPH E. FOSTER,
DAVID PLAQUIN, and JAMES M. MANN
Appeal 2019-004507
Application 15/518,218
Technology Center 2100
BEFORE JASON V. MORGAN, JEREMY J. CURCURI, and
PHILLIP A. BENNETT, Administrative Patent Judges.
CURCURI, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–3 and 5–15. We have jurisdiction
under 35 U.S.C. § 6(b).
We AFFIRM IN PART.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as Hewlett Packard
Enterprise Development LP. Appeal Br. 1.
Appeal 2019-004507
Application 15/518,218
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CLAIMED SUBJECT MATTER
The claims are directed to restricting write access to non-volatile
memory. Spec., Title. Claim 1, reproduced below, is illustrative of the
claimed subject matter:
1. A method for restricting write access to a non-volatile
memory, the method comprising:
routing read and write requests for an address or address
range corresponding to a protected location in the non-volatile
memory of a memory module including a media controller and
the non-volatile memory from a processing unit to the media
controller;
passing read and write requests for addresses other than
the address or address range corresponding to the protected
location from the processing unit directly to the non-volatile
memory;
receiving, by the media controller, a routed request to
write to the protected location in the non-volatile memory;
determining whether the protected location is in a write-
protected state;
if the protected location is not in a write-protected state,
writing data indicated by the routed request to the protected
location; and
if the protected location is in a write-protected state,
rejecting the routed request.
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REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Katayama US 5,938,758 Aug. 17, 1999
Kodama US 2005/0210211 A1 Sept. 22, 2005
Moore US 2012/0151126 A1 June 14, 2012
Dalcher US 8,561,204 B1 Oct. 15, 2013

REJECTIONS
Claims 1, 6, 9, and 11 are rejected under 35 U.S.C. § 102(a)(1) as
anticipated by Moore. Final Act. 2–3.
Claims 2, 3, 5, 7, 8, and 10 are rejected under 35 U.S.C. § 103 as
obvious over Moore and Dalcher. Final Act. 4–5.
Claims 12–14 are rejected under 35 U.S.C. § 103 as obvious over
Moore and Kodama. Final Act. 5–7.
Claim 15 is rejected under 35 U.S.C. § 103 as obvious over Moore,
Kodama, and Katayama. Final Act. 7–8.
OPINION
The Anticipation Rejection of Claims 1, 6, 9, and 11 by Moore
The Examiner finds Moore discloses all limitations of claim 1. Final
Act. 2–3. In particular, the Examiner finds Moore’s processor 302 describes
the “processing unit” recited in claim 1. Final Act. 2 (citing Moore, Fig. 3,
processor 302). The Examiner further finds Moore’s protection logic 206
and interface logic 208 describe the “media controller” recited in claim 1.
Final Act. 2 (citing Moore, Fig. 2, protection logic 206, interface logic 208).
The Examiner further finds Moore describes “passing read and write
requests for addresses other than the address or address range corresponding
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Application 15/518,218
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to the protected location from the processing unit directly to the non-volatile
memory” as recited in claim 1. Final Act. 3 (citing Moore, Fig. 2,
unprotected memory region 203, ¶ 24).
Appellant presents the following principal argument:
The interface 208 and the protection logic 206 [in Moore] have
been interpreted as the claimed media controller. Therefore, all
requests [in Moore] — including read/write requests for
addresses other than the address/address range corresponding to
the claimed protected NVRAM location (i.e., to the unprotected
region 203 [in Moore]) — are passed through the media
controller 206/208, and not directly to the NVRAM 202 as
claimed.
Appeal Br. 5 (citing Moore ¶ 24); see also Reply Br. 1 (“In Moore, in other
words, read and write requests for addresses other than the address or
address range corresponding to the protected region 204 are passed
indirectly from the processor 302 to the non-volatile memory 202, through
the media controller 206/208 of the USB drive 100.”)
In response, the Examiner explains “[t]he claim does not specify
which device is ‘directly’ passing the read and write requests to the non-
volatile memory.” Ans. 3.
Claim 1 recites “passing read and write requests for addresses other
than the address or address range corresponding to the protected location
from the processing unit directly to the non-volatile memory.” Claim 1
(emphasis added). Contrary to the Examiner, we interpret claim 1 as
requiring that requests are passed from the processing unit directly to the
non-volatile memory, without passing through an intermediary.
Given our interpretation of claim 1, we determine the Examiner erred
in finding Moore discloses “passing read and write requests for addresses
other than the address or address range corresponding to the protected
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location from the processing unit directly to the non-volatile memory” as
recited in claim 1.
Moore discloses “[i]nterface logic 208 receives data access requests
from both connectors 104 and 106.” Moore ¶ 24. Moore discloses “requests
are in the form of commands to write to or read data.” Moore ¶ 24. Moore
discloses “[d]ata write requests are received and the accompanying data is
stored in unprotected region 203 when that is the specified destination.”
Moore ¶ 24. Thus, we interpret Moore as describing interface logic 208
receiving (from processor 302) write requests for unprotected region 203.
This is contrary to our interpretation of claim 1 which requires that requests
be passed from the processing unit directly to the non-volatile memory,
without passing through an intermediary.
We, therefore, do not sustain the Examiner’s rejection of claim 1.
Independent claim 6 recites
a media controller coupled to the non-volatile memory and the
processing unit, read and write requests for an address or address
range corresponding to the protected location routed from the
processing unit to the memory controller, read and write requests
for addresses other than the address or address range
corresponding to the protected location passed directly to the
non-volatile memory.
Claim 6 (emphasis added). Unlike claim 1, claim 6 does not require that
requests be passed from the processing unit directly to the non-volatile
memory, without passing through an intermediary. See Ans. 3 (“The claim
does not specify which device is ‘directly’ passing the read and write
requests to the non-volatile memory.”). Accordingly, for claim 6, we
determine Appellant’s arguments are not commensurate with the scope of
the claim. We, therefore, sustain the Examiner’s rejection of claim 6. We
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also sustain the Examiner’s rejection of claims 9 and 11, which depend from
claim 6, and are not separately argued with particularity. See Appeal Br. 4.

The Obviousness Rejection of Claims 2, 3, 5, 7, 8, and 10 over Moore and
Dalcher
The Examiner does not find Dalcher overcomes the deficiency of
Moore. See Final Act. 4–5. We, therefore, do not sustain the Examiner’s
rejection of claims 2, 3, and 5, which depend from claim 1.
Appellant does not present separate arguments for claims 7, 8, and 10.
See Appeal Br. 6. We, therefore, sustain the Examiner’s rejection of claims
7, 8, and 10, which depend from claim 6.

The Obviousness Rejection of Claims 12–14 over Moore and Kodama
The Examiner finds Moore and Kodama teach all limitations of claim
12. Final Act. 5–7. Among other limitations, the Examiner finds Moore
teaches “initializing the log buffer by resetting each location within the
address range other than at the last address as not in a write-protected state,
and resetting a location at the last address as in the write-protected state” as
recited in claim 12. Final Act. 5 (citing Moore ¶ 23). The Examiner finds
Kodama teaches,
if the request is to write to the next address that is not in the write-
protected state, writing data indicated by the request to an
address indicated by a write next pointer, setting the location at
the next address as in the write-protected state, and incrementing
the write next pointer,
as recited in claim 12. Final Act. 6 (citing Kodama, Fig. 8, ¶¶ 2, 20).
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Appellant presents the following principal argument:
“Rather than initializing the location at the last address of the log
buffer as in a write-protected state (as claimed), the applied art initially has
all the locations within the address range of the log buffer — including the
location at the last address — as not write protected.” Appeal Br. 7 (citing
Kodama, Fig. 8).
In response, the Examiner explains
Moore states that the unprotected and protected regions 203/204
may be any size (see paragraph 0023). This could be taken to
mean that the unprotected region 203 is the entire memory 202,
with the exception of the last address, which would be the
protected region 204. In addition, Kodama also teaches the
argued feature. As shown in Figure 8, item 803 can be any size,
meaning that the unprotected region (read and write area) can be
all of the disk with the exception of the last address, which would
be the read-only area 803. Therefore, it can be seen that in both
references the last address may be write-protected, as claimed.
Ans. 4.
In reply, Appellant further argues the following:
[T]hat the unprotected and protected regions 203/204 [in Moore]
can be of any size does not rise to the level of teaching resetting
each location within an address range other than a last address as
not in a write-protected state and resetting the location at the last
address as in the write-protected state as claimed.
Reply Br. 3.
Kodama has to track the last location of a log buffer to ensure
that a buffer overflow condition does not result, and indeed does
so (see FIG. 3, as to ending offset). In this respect, then, Kodama
initially has all locations of the log buffer set to not write
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protected, per FIG. 8, and then sets them to write protected as
writing occurs.
Reply Br. 3.
“The applied art in combination has to check the address of a write
request to see if the address is past the last address of the buffer to protect
against buffer overflow, which claim 12 does not have to do.” Reply Br. 4.
Appellant’s arguments persuade us that the Examiner erred in finding
the applied references teach “initializing the log buffer by resetting each
location within the address range other than at the last address as not in a
write-protected state, and resetting a location at the last address as in the
write-protected state” as recited in claim 12.
Moore discloses “protection logic 206 is configured to partition
memory 202 into a protected region 204 and an unprotected region 203.”
Moore ¶ 23. To the extent that Moore’s protected region 204 and
unprotected region 203 could be any size (see Ans. 4), we do not agree with
the Examiner that such disclosure is sufficient to teach defining and
initializing a “log buffer” including “resetting a location at the last address
as in the write-protected state” as recited in claim 12. See Reply Br. 3 (“does
not rise to the level of teaching resetting”). Further, we determine Kodama
does not cure this deficiency in Moore.
Kodama reasonably describes a log buffer and a write next pointer
that points to a memory location. See Kodama, Fig. 8 (depicting the use of a
next write pointer 801 to implement write-once read-many (WORM)).
However, in Kodama, the last address is not initialized in a write-protected
state. See Kodama, Fig. 8 (disk block number 1024 is shown in read and
write area 804 as opposed to being read only). Thus, Kodama also does not
teach defining and initializing a “log buffer” including “resetting a location
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at the last address as in the write-protected state” as recited in claim 12. See
Reply Br. 3 (“Kodama initially has all locations of the log buffer set to not
write protected”).
In short, on this record, we do not readily see a suggestion by the
applied references to initialize the last address in the log buffer to the write-
protected state.
We, therefore, do not sustain the Examiner’s rejection of claim 12.
We also do not sustain the Examiner’s rejection of claims 13 and 14, which
depend from claim 12.

The Obviousness Rejection of Claim 15 over Moore, Kodama, and
Katayama
The Examiner does not find Katayama overcomes the deficiency of
Moore and Kodama. See Final Act. 7–8; see also Ans. 4–5. We, therefore,
do not sustain the Examiner’s rejection of claim 15, which depends from
claim 12.
CONCLUSION
The Examiner’s decision to reject claims 1–3, 5, and 12–15 is
reversed.
The Examiner’s decision to reject claims 6–11 is affirmed.

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Application 15/518,218
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DECISION SUMMARY
In summary:
Claims
Rejected
35
U.S.C. §
Reference(s) Affirmed Reversed
1, 6, 9, 11 102(a)(1) Moore 1 6, 9, 11
2, 3, 5, 7, 8, 10 103 Moore, Dalcher 2, 3, 5 7, 8, 10
12–14 103 Moore, Kodama 12–14
15 103 Moore, Kodama,
Katayama
15
Overall
Outcome
1–3, 5, 12–15 6–11

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED IN PART