Hewlett Packard Enterprise Development LP

Patent Trials and Appeals Board

Dec 11, 2020

2019004349 (P.T.A.B. Dec. 11, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/109,375 06/30/2016 Michael R. KRAUSE 90227423 2345
56436 7590 12/11/2020
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
EXAMINER
GEBRIL, MOHAMED M
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
12/11/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
chris.mania@hpe.com
hpe.ip.mail@hpe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte MICHAEL R. KRAUSE
Appeal 2019-004349
Application 15/109,375
Technology Center 2100
Before JUSTIN BUSCH, CARL L. SILVERMAN, and
STEVEN M. AMUNDSON, Administrative Patent Judges.
BUSCH, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–7 and 9–15. See Final Act. 1. We
have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the term “Appellant” to refer to “applicant” as defined in 37 C.F.R.
§ 1.42. Appellant identifies the real party in interest as Hewlett Packard
Enterprise Development LP. Appeal Br. 1.
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Application 15/109,375
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CLAIMED SUBJECT MATTER
The invention generally relates to memory management with respect
to data versions. Spec. ¶ 12. More specifically, the claimed subject matter
relates to providing access to multiple requestors in parallel to different
versions of data and “shuffling” access to the data versions across requestors
at different times by modifying a data structure. Spec. ¶¶ 35, 40, 63–66.
Claim 1, reproduced below, is illustrative of the claimed subject matter:
1. A method comprising:
receiving, by a memory management unit, a transaction
request to perform an operation with respect to data in memory,
the transaction request including control information;
identifying, by the memory management unit based on the
control information, one of a plurality of versions of a given
memory data, wherein the plurality of versions of the given
memory data include a first version of the given memory data
and a second version of the given memory data that is modified
from the first version;
accessing, by the memory management unit, the identified
version of the given memory data in response to the transaction
request, wherein the plurality of versions of the given memory
data are accessible by a plurality of requestors in parallel; and
shuffling the plurality of versions of the given memory
data across the plurality of requestors such that the plurality of
requestors access different ones of the plurality of versions of the
given memory data at different times, wherein the shuffling is
performed by modifying a translation data structure in the
memory management unit.
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CITED PRIOR ART
Name Reference Date
Ellis US 2003/0212859 A1 Nov. 13, 2003
Kandiraju US 2013/0332684 A1 Dec. 12, 2013
Talagala US 2013/0332660 A1 Dec. 12, 2013
REJECTIONS
Claims 1–7 and 10–13 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Kandiraju and Talagala. Final Act. 4–17.
Claims 9, 14, and 15 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Kandiraju, Talagala, and Ellis. Final Act. 17–22.
OPINION
The Examiner finds the combination of Kandiraju and Talagala
teaches or suggests every limitation recited in independent claims 1 and 10,
and the combination of Kandiraju, Talagala, and Ellis teaches or suggests
every limitation recited in independent claim 14. Final Act. 4–7, 12–15, 18–
22. Of particular relevance to this Appeal, the Examiner finds Talagala
teaches or suggests “shuffling the plurality of versions of the given memory
data across the plurality of requestors . . . wherein the shuffling is performed
by modifying a translation data structure in the memory management unit”
(the “disputed limitation”), as recited in independent claim 1 and
commensurately recited in independent claims 10 and 14. Final Act. 6 –7
(citing Talagala ¶¶ 45, 50, 62–63, 69, 183–185, Figs. 1–2), 14–15, 20–21.
Specifically, the Examiner finds Talagala teaches the recited shuffling
across a plurality of requestors because Talagala discloses a version module
that dynamically selects and loads various memory states and a memory
module that dynamically swaps and allocates volatile memory and non-
volatile storage media for storage clients. Final Act. 6–7 (citing Talagala
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¶¶ 45, 50, 62–63, 69, 185, Figs. 1–2); Ans. 22–23 (repeating the same
findings). The Examiner then finds Talagala teaches “shuffling is performed
by modifying a translation data structure” because Talagala discloses a
version module that provides access to subsequent versions of data by
cooperating with a namespace module that uses different persistent storage
namespace identifiers for each version by “iterating or updating the
persistent namespace identifier in response to each checkpoint trigger
event.” Final Act. 7 (citing Talagala ¶¶ 183–184, Figs. 1–2); Ans. 23
(repeating the same findings).
Among other arguments, Appellant asserts Talagala does not teach or
suggest the disputed limitation. Appeal Br. 8–10; Reply Br. 4–5. Appellant
argues Talagala’s disclosed data swapping from one memory hierarchy
location to another (e.g., from volatile to non-volatile or from non-volatile to
storage media) does not relate to shuffling versions of data across a plurality
of requestors and does not teach or suggest shuffling different data versions
by modifying a translation data structure. Appeal Br. 9–10; Reply Br. 4–5.
Appellant argues that swapping data from one memory type or location to
another relates to storage locations and is irrelevant to the claimed “shuffling
different versions” across requestors. Reply Br. 5. Appellant also argues
moving data from one memory location to another does not teach the recited
shuffling different versions by modifying a translation data structure, which
does not move the location at which the different versions are stored. Reply
Br. 5.
Neither Appellant nor the Examiner explicitly construe the disputed
limitation, but the Examiner’s findings and Appellant’s arguments rely on
implicit constructions. Claim construction is an important step in a
patentability determination. A legal conclusion that a claim is obvious
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involves a two-step inquiry wherein first, the claims are properly construed,
and second, the properly construed claims are compared to the prior art. See
Medichem, S.A. v. Rolabo, S.L., 353 F.3d 928, 933 (Fed. Cir. 2003); see also
In re Crish, 393 F.3d 1253, 1256 (Fed. Cir. 2004).
When construing claim terminology during prosecution before the
Office, claims are to be given their broadest reasonable interpretation
consistent with the Specification, reading claim language in light of the
Specification as it would be interpreted by one of ordinary skill in the art. In
re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). We
presume that claim terms have their ordinary and customary meaning. See
In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007) (“The
ordinary and customary meaning is the meaning that the term would have to
a person of ordinary skill in the art in question.”) (internal quotation marks
omitted).
In particular, we construe the disputed limitation, which recites
“shuffling the plurality of versions of the given memory data across the
plurality of requestors . . . wherein the shuffling is performed by modifying a
translation data structure in the memory management unit.” Other parts of
the claim recite that the “plurality of versions of the given memory data
include a first version of the given memory data and a second version of the
given memory data that is modified from the first version.” Accordingly,
the claim itself provides guidance regarding what is meant by the plurality of
versions in the disputed limitation—namely, that each one of the plurality of
versions is distinct from, but a variation of, the others of the plurality of
versions.
With that understanding, we first interpret what is meant by
“shuffling” these versions “across the plurality of requestors.” The
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subsequent claim language provides the only context necessary to properly
interpret this portion of the disputed limitation. Specifically, the claim
further recites that the shuffling is done “such that the plurality of requestors
access different ones of the plurality of versions of the given memory data at
different times,” which resolves any potential ambiguity regarding the
ordinary meaning of shuffling the versions across requestors. In other
words, shuffling the versions across the requestors means rearranging
requestors’ access so that a particular requestor accesses a first version at a
first point in time and a second version at a second point in time.
Next, we construe the latter portion of the disputed limitation, which
recites that “the shuffling is performed by modifying a translation data
structure in the memory management unit.” We note that, importantly, the
disputed limitation clearly recites that “modifying a translation data
structure” is how the system performs the “shuffling action” that is
responsible for rearranging the versions that the requestors access.
Our understanding is supported by the Specification, which discloses
that one example of a translation data structure is an index. Spec. ¶ 31
(referring to index 109 in Figure 1). The Specification further discloses that
the memory management unit may look up the index based on received
control information, such as an identifier, in order to “produce[] a respective
physical resource address.” Spec. ¶ 31; id. ¶ 66 (“The mapping between
requestors 1, 2, 3, and 4, and respective data versions A, B, C, and D” can
change, and “[e]ach requestor can be associated with a respective unique
SSID; the different SSIDs can be mapped by the memory management unit
104 to different ones of the data versions.”). An example of performing
“shuffling . . . by modifying a translation data structure,” as recited, involves
dynamically changing the index “such that the mapping between control
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information and data versions can change over time.” Spec. ¶ 31; id. ¶ 66
(“The shuffling can be performed by modifying a translation data structure
(e.g. index 109 in Fig. 1) in the memory management unit 104, for
example.”). In order to track the versions, every time a new data version is
created, “the memory management unit 104 allocates a corresponding
memory resource in the memory 102, and updates content of various data
structures in the memory management unit 104, such as the address mapping
tables and the index used by the address translator 108.” Spec. ¶ 34.
Consistent with the disputed limitation’s plain language and the
Specification, we construe the disputed limitation as modifying a translation
data structure that causes the system to rearrange which requestors access
which versions of data such that a particular requestor accesses one version
at a first point in time and a different version at a second point in time.
Based on our construction of the disputed limitation, we consider the
Examiner’s rejection problematic. As discussed above, the Examiner finds
Talagala teaches or suggests the first portion of the limitation—“shuffling
the plurality of versions of the given memory data across the plurality of
requestors such that the plurality of requestors access different ones of the
plurality of versions of the given memory data at different times.” We
understand the Examiner to find that (1) Talagala teaches shuffling versions
because Talagala’s memory module swaps memory (including the different
versions) between different types of storage and (2) Talagala teaches
requestors accessing different versions at different times because Talagala’s
version module loads dynamically selects and loads different versions (i.e.,
memory states) at different times. See Final Act. 6–7; Ans. 22–23.
We agree that Talagala separately teaches (1) a memory module that
shuffles versions of memory data because the memory module moves
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versions of memory data between different storage types and (2) a version
module that lets requestors access different versions of the memory data at
different times. See Talagala ¶¶ 69 (disclosing that an extended memory
module may dynamically swap or move data between different levels of a
memory hierarchy), 45 (disclosing the ability to store multiple versions,
including valid and invalid versions), 106 (disclosing that different versions
or copies may be independently accessible using different identifiers), 183–
185 (disclosing storing multiple checkpoints for the same range of memory
addresses and providing access to different versions of the data at that range
of virtual memory using different identifiers and dynamically selecting and
loading various memory states). The Examiner’s findings, however, fail to
address that the claim recites that the “shuffling” is done “such that the
plurality of requestors access different ones of the plurality of versions of the
given memory data at different times.” In other words, we disagree that
Talagala’s cited portions teach or suggest rearranging requestors’ access so
that a particular requestor accesses a first version at a first point in time and
a second version at a second point in time because Talagala does not teach
that the memory manager swaps or moves data between levels so that the
version manager provides different versions to requestors at different times.
Moreover, even assuming Talagala somehow suggested a relationship
between moving or swapping between memory hierarchies to provide
different versions of data to requestors at different times, we disagree that
Talagala teaches or suggests the second portion of the disputed limitation—
“the shuffling is performed by modifying a translation data structure in the
memory management unit.” As mentioned above, the Examiner finds
Talagala teaches this feature because Talagala discloses a version module
that provides access to subsequent versions of data by cooperating with a
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namespace module that uses different persistent storage namespace
identifiers for each version by “iterating or updating the persistent
namespace identifier in response to each checkpoint trigger event.” Final
Act. 7; Ans. 23. Based on the Examiner’s findings and conclusions, the
Examiner’s implicit construction appears to ignore the link between the
shuffling action and the action of modifying a translation data structure.
More specifically, even accepting the Examiner’s finding that Talagala
teaches shuffling versions of memory data across requestors because
Talagala’s memory module moves or swaps memory data, we see no tie
between Talagala’s module that moves or swaps memory and the cited
namespace module that assigns namespace identifiers to the Talagala’s
different data versions. The rejection correctly finds Talagala assigns
namespace identifiers to different versions by updating or iterating a
namespace identifier. See Talagala ¶ 183. However, the rejection fails to
support a finding that the memory module swapping memory data, which
the Examiner finds teaches the recited shuffling, is performed by (or
otherwise related to) iterating or updating a namespace identifier, which the
Examiner finds teaches the recited “modifying a translation data structure.”
See Final Act. 6–7.
CONCLUSION
For the above reasons, on this record, we do not sustain the rejection
of independent claims 1 and 10, which recite the disputed limitation, as
obvious over Kandiraju and Talagala. Nor do we sustain the rejection of
claims 2–7 and 11–13, which depend therefrom and incorporate the disputed
limitation, under 35 U.S.C. § 103 as obvious over Kandiraju and Talagala.
The Examiner does not find Ellis cures this deficiency. Therefore we do not
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sustain the rejection of independent claim 14, which recites the disputed
limitation, claim 9, which depends from claim 1 thereby incorporating the
disputed limitation, and claim 15, which depends from claim 14 thereby
incorporating the disputed limitation, under 35 U.S.C. § 103 as obvious over
Kandiraju, Talagala, and Ellis.
DECISION SUMMARY
Claim(s)
Rejected
35 U.S.C. § Reference(s) Affirmed Reversed
1–7, 10–13 103 Kandiraju, Talagala 1–7, 10–13
9, 14, 15 103 Kandiraju, Talagala,
Ellis
9, 14, 15
Overall
Outcome
1–7, 9–15

REVERSED