HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Patent Trials and Appeals Board

Aug 10, 2020

2019006117 (P.T.A.B. Aug. 10, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/314,831 11/29/2016 Lidia Warnes 90310356 1043
56436 7590 08/10/2020
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
EXAMINER
BASHAR, MOHAMMED A
ART UNIT PAPER NUMBER
2824
NOTIFICATION DATE DELIVERY MODE
08/10/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
chris.mania@hpe.com
hpe.ip.mail@hpe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte LIDIA WARNES, MELVIN K. BENEDICT, and
ANDREW C. WALTON
Appeal 2019-006117
Application 15/314,831
Technology Center 2800
Before CATHERINE Q. TIMM, CHRISTOPHER C. KENNEDY, and
JEFFREY R. SNAY, Administrative Patent Judges.
TIMM, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–20. See Final Act. 1. We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM IN PART.

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as Hewlett
Packard Development LP. Appeal Br. 1.
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Application 15/314,831
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CLAIMED SUBJECT MATTER
The claims are directed to a memory module (see, e.g., claim 1), a
machine readable storage medium (see, e.g., claim 6), and a method of
initiating a post package repair (PPR) on a memory device in response to the
number of errors on the memory device (see, e.g., claim 12). We reproduce
claims 1, 6, and 12 below with highlighting to emphasize the limitations at
issue:
1. A memory module comprising:
a repair unit; and
a memory device having on-die error-correcting code
(ECC), wherein:
the memory device comprises a plurality of
memory units and a plurality of error counters;
one of the plurality of error counters is to count
errors, detected by the on-die ECC, in a first memory unit
of the plurality of memory units;
a post package repair (PPR) is initiated on the memory
device in response to a determination that a value of the one of
the plurality of error counters equals a threshold value; and
during the PPR, data in the first memory unit is copied to
the repair unit.
Appeal Br. 23 (Claims Appendix) (emphasis added).
6. A machine-readable storage medium encoded with
instructions executable by a processor, the machine-readable
storage medium comprising:
instructions to determine whether a value of one of a
plurality of error counters on a memory device equals a
threshold value, wherein:
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the memory device comprises on-die error-
correcting code (ECG);
the one of the plurality of error counters is
associated with a memory unit on the memory device;
and
the one of the plurality of error counters is to be
incremented in response to an error being detected, by
the on-die ECG, in the memory unit; and
instructions to initiate, in response to a determination
that the value of the one of the plurality of error counters
equals the threshold value, a post package repair (PPR),
wherein the PPR comprises replacing the memory unit with a
repair unit.
Appeal Br. 24–25 (Claims Appendix) (emphasis added).
12. A method comprising:
incrementing, in response to detection of an error in one
of a plurality of memory units on a memory device, an error
counter on the memory device, wherein:
the error is detected by on-die error-correcting
code (ECC) on the memory device; and
the error counter is associated with the one of the
plurality of memory units;
performing, in response to a determination that a value
of the error counter exceeds a threshold value, a post package
repair (PPR) on the memory device; and
copying, during the PPR, data in the one of the plurality
of memory units to a repair unit.
Amendment filed April 12, 20182 (emphasis added).

2 We reproduce the claim from Amendment of April 12, 2018 because the
copy of the claim in the Claims Appendix to the Appeal Brief contains a
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Application 15/314,831
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REJECTION
The Examiner rejects claims 1–20 under 35 U.S.C. § 103 as obvious
over Jeong.3
OPINION
Appellant argues the claims under separate headings. Appeal Br. 4–
21. To the extent required, we address each claim or group of claims
separately.
Claim 1
Appellant presents two arguments against the Examiner’s rejection of
claim 1: (1) that Jeong fails to disclose the claimed “repair unit” and (2) that
Jeong fails to disclose the last two steps recited in claim 1. Appeal Br. 5–7.
We do not find these arguments persuasive of reversible error in the
Examiner’s rejection of claim 1 for the following reasons.
Repair Unit
The Examiner finds that Jeong’s error corrector 136, comparator 138,
and input/output buffer 140 is a repair unit within the meaning of
Appellant’s claim 1. Final Act. 3. Appellant contends the Specification
defines “repair units” as redundant memory elements and Jeong’s units 136,
138, and 140 are not redundant memory elements. Appeal Br. 5.
The first issue is whether “repair unit” as used in the claim is limited
to redundant memory elements. We agree with the Examiner that it is not.
The Specification does not define “repair unit” with the reasonable clarity,
deliberateness, and precision necessary to give notice to the ordinary artisan

typographical error, i.e., it contains the word “equal” after “exceeds.” As
shown in the Amendment, “equal” was deleted and replaced with “exceeds.”
3 Jeong et al., US 2015/0162099 A1, published June 11, 2015.
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that the term is so limited. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir.
1994) (quoting Intellicall, Inc. v. Phonometrics, Inc, 952 F.2d 1384, 1378–
88 (Fed. Cir. 1992)) (“Although an inventor is indeed free to define the
specific terms used to describe his or her invention, this must be done with
reasonable clarity, deliberateness, and precision.”). The Specification merely
states that “redundant memory elements may be referred to herein as ‘repair
units’.” Spec. ¶ 11 (emphasis added). As Appellant has not stated that they
are using the term “repair elements” to refer only to redundant memory
elements and Appellant is free to amend the claim to use the redundant
memory element language, we agree with the Examiner that “repair unit”
can be reasonably interpreted to refer to any unit that performs a repair
function.
Appellant does not dispute that Jeong’s units 136, 138, and 140
perform a repair function. Jeong specifically terms unit 136 an error
corrector that corretcs an error. Jeong ¶ 46. Moreover, the Examiner points
out that, in fact, Jeong teaches a redundant memory element. Ans. 4–5; see
also Jeong ¶¶ 91–93.
Appellant has not persuaded us that the Examiner reversibly erred in
the finding that Jeong teaches a repair unit as required by claim 1.
Last Two Steps
Appellant points out that Jeong fails to disclose correcting errors in
response to the number of errors equaling a threshold value and copying data
in the first memory unit to the repair unit during the error correction process
(post package repair (PPR)). Appeal Br. 6–7.
For claim 1, we find this argument unpersuasive because claim 1 is
directed to a memory module, a “manufacture,” according to the statutory
classes of 35 U.S.C. § 101, and claim 1 does not contain any affirmative
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structure for carrying out the post package repair and copying steps. These
steps appear to be carried out using instructions on for instance, a machine-
readable storage medium. See claim 6; Spec. ¶¶ 25, 33. The affirmatively
claimed structural components recited in claim 1 are a repair unit and a
memory device with on-die error-correcting code, a plurality of memory
units, and a plurality of error counters. Jeong contains the structure
affirmatively recited in claim 1.
It has long been held that “apparatus claims cover what a device is,
not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909
F.2d 1464, 1468 (Fed. Cir. 1990). Patentability of the memory module
cannot turn on the use or function of the structure. In re Michlin, 256 F.2d
317, 320 (CCPA 1958) (“It is well settled that patentability of apparatus
claims must depend upon structural limitations and not upon statements of
function.”). Here, there is no convincing evidence that how the repair is
initiated or how the data is copied patentably distinguishes the memory
module structurally from the memory module suggested by Jeong.
Thus, we are not persuaded that the Examiner reversibly erred in
rejecting claim 1.
Claims 2 and 19
Claim 2 depends from claim 1 and further requires each of the
plurality of error counters be associated with a respective one of the plurality
of memory units. Claim 19 also depends from claim 1. Claim 19 further
requires each of the memory units comprise memory elements and wherein
each of the plurality of memory units is assigned one of the plurality of error
counters.
We agree with Appellant that “respective” requires each error counter
be associated with one memory unit. Reply Br. 5. In other words, claim 2
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requires pairings between the error counters and memory units. This reading
of “respective” is supported by the Specification, which discloses that
“[e]ach of error counters 108a, 108b, and 108c [shown in Figure 1] may
count errors, detected by on-die ECC 110, in a respective memory unit on
memory device 104. For example, error counter 108a may count errors,
detected by on-die ECC 110, in memory unit 106a.” Spec. ¶ 16. There must
be a one-to-one association between error counters and memory units.
Moreover, claim 19 similarly requires each of the plurality of memory units
is assigned one of the plurality of error counters. Thus, claim 19 similarly
requires a one-to-one assignment.
However, Appellant has not persuaded us that the Examiner erred in
finding that Jeong’s Figure 6 embodiment has the necessary structure. The
Examiner points out that Jeong’s Figure 6 embodiment includes a first
counter 343 associated with sense-amp SA1, which is coupled to first
memory unit 111 (Fig. 1) and a second counter 344 associated with sense-
amp SA2, which is coupled to second memory unit 112 (Fig. 1). Ans. 8; see
also Jeong ¶¶ 78–79. Appellant acknowledges that Jeong teaches two
counters (first error counter 343 and second error counter 344), but
Appellant contends that Jeong nowhere discloses that counters 343, 344 are
associated with respective ones of the plurality of memory units. Reply Br.
4. But Appellant’s contention ignores the Examiner’s finding that the sense-
amps SA1 and SA2 shown in Figure 6 are connected to respective memory
cells as shown in Figure 1. Thus, Appellant has not persuaded us of
reversible error in the Examiner’s rejection.
Claim 3
Claim 3 requires a register that stores a memory address that is
common to the plurality of memory elements. The Examiner finds that
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Jeong teaches the required register. Ans. 8, citing Jeong Figs. 1, 9, and 15;
¶¶ 48, 114. Appellant does not respond to the Examiner’s specific findings
in the Reply Brief. Reply Br. 4–5. Thus, Appellant has not identified a
reversible error in the Examiner’s findings.
Claim 4
Claim 4 recites actions taken in response to a determination that the
on-die ECC has not detected errors in the first memory for a predetermined
amount of time, but claim 4 does not recite additional memory module
structure. Thus, we are not persuaded of reversible error in the rejection.
Claim 5
Claim 5 depends from claim 1 and further requires that any of the
plurality of error counters be capable of counting errors, detected by the on-
die ECC, in any of the plurality of memory units; and further recites that the
plurality of error counters be assigned to respective ones of the plurality of
memory units in a first-in, first-out (FIFO) manner.
The Examiner finds that Jeong discloses error counters capable of
functioning as claimed in the embodiment of Figure 6. Ans. 9–10. This
embodiment includes two different counters 343, 344, one connected to first
memory unit 111 and one connected to second memory unit 112. Jeong
¶¶ 78, 79. The Examiner further finds that Jeong’s counters are assigned in a
first-in first-out (FIFO) manner. Id.
Appellant contends that “what the Examiner describes is not the
assignment of error counters to a plurality of memory units in a first-in first
out manner.” Reply Br. 8. But the question is not whether the counters
operate in the manner recited in the claim, but whether Jeong’s counters
have the structure required by the claim. Appellant has not persuaded us of a
difference in structure.
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Claim 16
Claim 16 depends from claim 1 and requires that the repair unit
comprise a redundant group of memory elements. The Examiner finds that
the embodiments of Jeong’s Figures 8–9 and 12 conduct a redundancy repair
using a repair unit that comprises a redundant group of memory elements.
Final Act. 9. Appellant contends that the Examiner has incorrectly
characterized what is actually disclosed by Jeong and that none of the
figures or paragraphs cited by the Examiner disclose a repair unit comprising
a redundant group of memory elements. Appeal Br. 19–20.
Appellant’s argument is not persuasive because the portions cited by
the examiner disclose performing a redundancy repair. For instance, Jeong
discloses that in the embodiment of Figures 8 and 9, test circuit 330
conducts a redundancy repair. Jeong ¶¶ 87–91. Appellant has not explained
why this does not meet the requirements of claim 16.
Claim 20
Claim 20 depends from claim 1 and recites that the PPR is not
initiated on the memory device in response to a determination that the value
of the one of the plurality of error counters is less than the threshold value.
However, as we explained above in reference to claim 1, there is no
convincing evidence that how the repair is initiated patentably distinguishes
the memory module structurally from the memory module suggested by
Jeong.
Claims 6 and 12
Claim 6 is directed to a machine-readable storage medium encoded
with instructions executable by a process and requires “instructions to
initiate, in response to a determination that the value of the one of the
plurality of error counters equals the threshold value, a post package repair
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(PPR), wherein the PPR comprises replacing the memory unit with a repair
unit.”
Jeong does not include the instructions required by claim 6. Instead of
initiating a post package repair when “the value of the one of the plurality of
error counters equals the threshold value,” Jeong initiates a repair “[w]hen
the number of errors thus counted or the number of errors thus adjusted is
smaller than a predetermined and/or desired value.” Jeong ¶ 46 (emphasis
added).
The Examiner’s interpretation of “threshold value” is unreasonable. A
threshold is not any value or a range (Ans. 5), it is predetermined value set
by the system. Jeong sets such a predetermined value (Jeong’s
“predetermined and/or desired value”), but Jeong does not instruct the
system to conduct a repair when this value is reached. Because the
instructions differ from those of Jeong and the Examiner has not established
that it would have been obvious to include the instructions required by claim
6, the Examiner has not established a case of obviousness over Jeong.
Claim 12 is directed to a method and requires a step of “performing,
in response to a determination that a value of the error counter exceeds a
threshold value, a post package repair (PPR) on the memory device.”
Because Jeong teaches performing the repair when the number of errors is
smaller than the predetermined value, Jeong does not teach the step required
by claim 12.
We agree with Appellant that the Examiner reversibly erred in
rejecting claims 6 and 12 as obvious over Jeong. Thus, we do not sustain the
rejection of claims 6 and 12 or the rejection of the claims that depend from
claims 6 or 12.
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CONCLUSION
The Examiner’s decision to reject claims 1–5, 16, 19, and 20 is
affirmed, but the Examiner’s decision to reject claims 6–15, 17, and 18 is
reversed.
DECISION SUMMARY
Claim(s)
Rejected
35 U.S.C. § Basis/Reference(s) Affirmed Reversed
1–20 103(a) Jeong 1–5, 16,
19, 20
6–15, 17, 18

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED IN PART