Hewlett Packard Enterprise Development LP

Patent Trials and Appeals Board

Dec 23, 2020

2019004531 (P.T.A.B. Dec. 23, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/710,492 05/12/2015 Kirill Malkin 90404689 8398
56436 7590 12/23/2020
Hewlett Packard Enterprise
3404 E. Harmony Road
Mail Stop 79
Fort Collins, CO 80528
EXAMINER
BIRKHIMER, CHRISTOPHER D
ART UNIT PAPER NUMBER
2136
NOTIFICATION DATE DELIVERY MODE
12/23/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
chris.mania@hpe.com
hpe.ip.mail@hpe.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte KIRILL MALKIN
____________

Appeal 2019-004531
Application 14/710,492
Technology Center 2100
____________

Before JAMES B. ARPIN, IRVIN E. BRANCH, and
PHILLIP A. BENNETT, Administrative Patent Judges.

ARPIN, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) the Examiner’s rejection
of claims 1, 2, 4–10, 12, 13, 15–21, 23, and 24, all of the pending claims.
Final Act. 2.2 Claims 3, 11, 14, and 22 are canceled. Appeal Br. 18, 20, 22,

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42. Appellant
identifies the real party-in-interest as Hewlett Packard Enterprise
Development LP, a wholly owned affiliate of Hewlett Packard
Enterprise. The general or managing partner of Hewlett Packard Enterprise
Development LP is Enterprise DC Holdings LLC. Appeal Br. 3.
2 In this Decision, we refer to Appellant’s Appeal Brief (“Appeal Br.,” filed
February 8, 2019) and Reply Brief (“Reply Br.,” filed May 21, 2019); the
Final Office Action (“Final Act.,” mailed September 12, 2018) and the
Examiner’s Answer (“Ans.,” mailed March 21, 2019); and the Specification
(“Spec.,” filed May 12, 2015). Rather than repeat the Examiner’s findings
and Appellant’s contentions in their entirety, we refer to these documents.
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24 (Claims App.). We have jurisdiction under 35 U.S.C. § 6(b).
We reverse.
STATEMENT OF THE CASE
Appellant’s claimed methods, first computing devices, and computer-
readable media “relate[] to software stacks. More specifically, the present
invention relates to a more efficient manner of writing into a shared memory
device while minimizing potential conflicts between two simultaneous
accesses into the same memory location.” Spec. ¶ 1.
As noted above, the Examiner rejects claims 1, 2, 4–10, 12, 13, 15–
21, 23, and 24. Claims 1, 12, and 23 are independent. Appeal Br. 17
(claim 1), 20–21 (claim 12), 24–25 (claim 23) (Claims App.). Claim 1
recites “[a] method for coordinating reading and writing processes among
computing devices sharing a memory device,” claim 12 recites “[a] first
computing device comprising: a processor and a memory storing instructions
that when executed by the processor cause the processor to” perform steps
substantially as recited in claim 1, and claim 23 recites “[a] non-transitory
computer readable medium storing instructions that when executed by a
processor cause the processor to” perform steps as recited in claim 12. Id.
Claims 2 and 4–10 depend directly or indirectly from claim 1, claims 13 and
15–21 depend directly or indirectly from claim 12, and claim 24 depends
directly from claim 23. Id. at 17–25.
Claim 1, reproduced below with disputed limitations emphasized, is
representative.
1. A method for coordinating reading and writing processes
among computing devices sharing a memory device, the method
comprising:
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identifying, by a first computing device of the computing
devices, a total number of the computing devices to store data in
the memory device;
creating, by the first computing device, a number of
subdivisions within the memory device corresponding to the
total number of the computing devices to store data in the
memory device;
assigning, by the first computing device, each of the
subdivisions within the memory device to only one of the
computing devices, wherein the assigned computing device of
one of the subdivisions is an owner of the subdivision and is the
only computing device allowed to write or modify data in the
subdivision, and other computing devices not assigned to the
subdivision are not allowed to write or modify the data in the
subdivision; and
in response to a request to read data in a first subdivision
that is assigned to the first computing device, wherein the request
is from one of the computing devices not assigned to the first
subdivision, allowing the requesting computing device that is not
assigned to the first subdivision to read the data in the first
subdivision without changing ownership or assignment of the
first subdivision based on a determination that the request to read
the data in the first subdivision by the requesting computing
device includes information correctly identifying the first
computing device as the owner of the first subdivision.
Id. at 17 (emphasis added).

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REFERENCES AND REJECTIONS
The Examiner relies upon the following references in rejecting the
pending claims:
Name3 Number Issued/Publ’d Filed
Jain US 6,484,185 B1 Nov. 19, 2002 Apr. 5, 1999
Aguilar US 2008/0155203 A1 June 26, 2008 Mar. 4, 2008
Jeong US 2009/0019248 A1 Jan. 15, 2009 Sept. 18, 2008
Peters US 2014/0359248 A1 Dec. 4, 2014 Sept. 6, 2013
The Examiner rejects claims 1, 2, 4, 7–9, 12, 13, 15, 18–20, 23, and
24 under 35 U.S.C. § 103 as obvious over the combined teachings of Jeong
and Aguilar (Final Act. 3–15); claims 10 and 21 under 35 U.S.C. § 103 as
obvious over the combined teachings of Jeong, Aguilar, and Peters (id. at
15–17, 18–19, 22–23); and claims 5, 6, 16, and 17 under 35 U.S.C. § 103 as
obvious over the combined teachings of Jeong, Aguilar, and Jain (id. at 17–
18, 19–22).
We review the appealed rejections for error based upon the issues
identified by Appellant, and in light of the contentions and evidence
produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential). Arguments not made are waived. See 37 C.F.R.
§ 41.37(c)(1)(iv). Appellant and the Examiner focus their findings and
contentions on claim 1; so do we. Appeal Br. 8–13; Ans. 4–18; Reply
Br. 2–6. Because we determine that reversal of the rejection of independent
claim 1 is dispositive, except for our ultimate decision, we do not discuss the

3 All reference citations are to the first named inventor only.
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merits of the rejections of claims 2, 4–10, 12, 13, 15–21, 23, and 24 further
herein. We address the rejections below.
ANALYSIS
1. Obviousness of Claim 1 Over Jeong and Aguilar
As noted above, the Examiner rejects independent claim 1 as obvious
over the combined teachings of Jeong and Aguilar. Final Act. 3–6. Claim 1
recites,
assigning, by the first computing device, each of the
subdivisions within the memory device to only one of the
computing devices, wherein the assigned computing device of
one of the subdivisions is an owner of the subdivision and is the
only computing device allowed to write or modify data in the
subdivision, and other computing devices not assigned to the
subdivision are not allowed to write or modify the data in the
subdivision.
Appeal Br. 17 (Claims App.) (emphases added). The Examiner finds Jeong
teaches or suggests this limitation. Final Act. 4 (citing Jeong ¶¶ 34, 39–44,
71, 87–90, Figs. 3 (reference numerals 210, 220, and 310), 4 (reference
numerals 440, 450, and 460)). In particular, the Examiner finds, “[t]he
common storage block is assigned to [whichever] processor is currently
accessing the common storage block. Each computing device has the sole
ability to write or modify data in a subdivision that is currently assigned to
the computing device.” Id. We disagree.
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Jeong’s Figure 4 is reproduced below.

Figure 4 depicts a conceptual diagram of how the storage block of memory
unit 310 is partitioned in accordance with an embodiment of Jeong’s
disclosure. Jeong ¶ 51. In particular, Jeong explains:
The storage block of the memory unit 310 can be
partitioned to partitions corresponding to the number of
processors coupled to the memory unit 310. This is to allow each
processor to access each partition at the same time to write or
read data. For example, in case 2 processors are coupled to the
memory unit 310, the memory unit 310 can be partitioned to at
least 2 blocks (i.e. a first storage block 440 and a second storage
block 460), and each of the partitioned blocks can be assigned to
be dedicated for each processor. Therefore, it is possible that
each processor accesses the storage block, assigned to be
dedicated for the processor, through the assigned port to
write/read the data.
Id. ¶ 70 (emphasis added); cf. Appeal Br. 17 (Claims App.) (“the assigned
computing device of one of the subdivisions is an owner of the subdivision
and is the only computing device allowed to write or modify data in the
subdivision, and other computing devices not assigned to the subdivision are
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not allowed to write or modify the data in the subdivision” (emphasis
added)).
Further, Jeong explains:
Although the memory unit 310 [cannot] be simultaneously
accessed by a plurality of processors 210 and 220, the memory
unit 310 can be partitioned to further comprise a common storage
block 450 that can be accessed by each processor at different
times. In other words, the common storage block 450 can be
individually accessed as long as it is not assigned to be a
dedicated block for a specific processor and it is not
simultaneously accessed. This is to maintain the temporal
consistency of the data consecutively by setting a process to be
completed before the next process starts. Of course, the memory
unit 310 can be partitioned to 3 or more blocks even though only
2 processors are coupled to the memory unit 310.
Jeong ¶ 71 (emphasis added); see id. ¶ 67 (“The memory unit 310 is
structured to be shared by a plurality of processors coupled to the memory
unit 310 . . .”).
Appellant contends,
the “common” storage block 450 in Jeong is not equivalent to a
“subdivision” recited in independent claim 1 because the
common storage block 450 is not assigned to only one computing
device, as recited in independent claim 1 (claim 1 recites,
“assigning, by the first computing device, each of the
subdivisions within the memory device to only one of the
computing devices”). Instead, the common storage block 450 of
Jeong is not assigned to any particular processor.
Appeal Br. 10 (emphasis added); see Reply Br. 3 (citing Jeong ¶¶ 70, 71).
Moreover, because Jeong teaches that any processor may write or modify
data in the common storage block, no processor is the “owner” of the
common storage block as “owner” is recited in claim 1. See Jeong ¶¶ 93,
103–105, Fig. 6 (reference numeral 515). Because either of Jeong’s
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processors 210 and 220 can access data in common storage block 450 and
neither of Jeong’s processors 210 and 220 is the “owner” of common storage
block 450, Appellant contends Jeong does not teach this limitation of
claim 1. See Appeal Br. 10. We agree with Appellant.
The Examiner finds,
the common storage block 450 is only assigned to a one
computer device at a time. The assigned computing device is the
computing device that is actually accessing the common storage
block. There is no requirement in the claim that the assignment
is not able to be changed over time, only that the storage block is
assigned to only one storage block at a given moment of time.
Final Act. 23–24; see Ans. 10–12. Nevertheless, the Specification explains:
The method includes assigning each compute device their own
respective memory location within a storage device that only that
particular compute device can, for example, write into or modify.
By assigning ownership to a particular memory location to one
compute device, the method reduces potential conflicts between
simultaneous accesses into the same memory location. The
ownership can also be used to determine when the data stored in
a particular memory location has been last updated in order to
ensure that a most current read of the data is being obtained.
Spec. ¶ 5 (emphasis added); see id. ¶¶ 30–32 (discussing problems with
alternating access over time), 38 (“For this scenario, it may be possible to
have one compute device be assigned to more than one unique subdivision.
Each unique subdivision, however, will still only possess one owner that has
the ability to write or modify the data stored in memory locations within the
unique subdivision.”). The Examiner’s interpretation of claim 1 is contrary
to the plain meaning of the language of the disputed limitation, as
understood in view of the Specification, and the Examiner cites no
disclosure from the Specification supporting its interpretation.
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Further, claim 1 recites, in response to a request from a non-owner
computing device for access to a first computing device’s assigned first
subdivision, “allowing the requesting computing device that is not assigned
to the first subdivision to read the data in the first subdivision without
changing ownership or assignment of the first subdivision.” Appeal Br. 17
(Claims App.) (emphases added). Although the Examiner relies on Aguilar,
not Jeong, to teach or suggest this limitation,4 when interpreting the claim
limitations, we do not consider the claim limitations “in a vacuum, devoid of
the context of the claim as a whole.” Kyocera Wireless Corp. v. Int’l Trade
Comm’n, 545 F.3d 1340, 1347 (Fed. Cir. 2008); see McRO, Inc. v. Bandai
Namco Games America Inc., 959 F.3d 1091, 1097 (Fed. Cir. 2020) (“The
proper claim construction is based ‘not only in the context of the particular
claim in which the disputed term appears, but in the context of the entire
patent, including the specification.’”). Considering the claim as a whole, we
find the Examiner’s interpretation of assigning only temporary ownership of
a subdivision to a computing device contrary to the language of the disputed
limitation, read alone and in context, and to the Specification’s disclosure.
Because we are persuaded the Examiner misinterprets the disputed
limitation of claim 1 and, thus, misapplies Jeong’s teachings to that
limitation, we are persuaded that the Examiner errs in rejecting claim 1.
Consequently, we do not sustain the obviousness rejection of claim 1.
Because the Examiner’s failure to show that Jeong teaches or suggests the
disputed limitation of claim 1 is dispositive error, we do not reach

4 Final Act. 5 (citing Aguilar ¶¶ 105–108, Figs. 26, 28 (reference numerals
1722, 1732, 1740)).
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Appellant’s other contentions allegedly distinguishing claim 1 over the
combined teachings of Jeong and Aguilar.
2. The Remaining Claims
Claims 12 and 23 include limitations corresponding to the disputed
limitations of claim 1. Appellant challenges the rejection of independent
claims 12 and 23 for substantially the same reasons as claim 1. Appeal
Br. 7. For the reasons given above with respect to claim 1, we also do not
sustain the rejection of independent claims 12 and 23.
Each of claims 2, 4–10, 13, 15–21, and 24 depends directly from
independent claim 1, 12, or 23. Id. at 17–25 (Claims App.). Our reversal of
the Examiner’s rejection of independent claims 1, 12, and 23 is dispositive
with respect to the dependent claims. Id. at 14–15; see Reply Br. 6.
Because we are persuaded the Examiner errs with respect to the obviousness
rejection of claims 1, 12, and 23, we also are persuaded the Examiner errs
with respect to the obviousness rejections of claims 2, 4–10, 13, 15–21, and
24. For this reason, we do not sustain the rejections of the dependent claims.
DECISION
1. The Examiner errs in rejecting claims 1, 2, 4–10, 12, 13, 15–21, 23,
and 24 under 35 U.S.C. § 103 as rendered obvious over the combined
teachings of Jeong and Aguilar, alone or in combination with Peters or
Jain.
2. Thus, on this record, claims 1, 2, 4–10, 12, 13, 15–21, 23, and 24 are
not unpatentable.
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CONCLUSION
For the above reasons, we reverse the Examiner’s decision rejecting
claims 1, 2, 4–10, 12, 13, 15–21, 23, and 24.
In summary:
Claims
Rejected
35
U.S.C. §
Reference(s)/Basis Affirmed Reversed
1, 2, 4, 7–9,
12, 13, 15,
18–20, 23,
24
103 Jeong, Aguilar

1, 2, 4, 7–9,
12, 13, 15,
18–20, 23,
24
10, 21 103 Jeong, Aguilar,
Peters
10, 21
5, 6, 16, 17 103 Jeong, Aguilar,
Jain
5, 6, 16, 17
Overall
Outcome
1, 2, 4–10,
12, 13, 15–
21, 23, 24
REVERSED