Gong, Haiyan et al.

Patent Trials and Appeals Board

Feb 12, 2020

14160706 - (D) (P.T.A.B. Feb. 12, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/160,706 01/22/2014 Haiyan Gong 13-SC-0825-US01 1028
102469 7590 02/12/2020
PARKER JUSTISS, P.C./Nvidia
14241 DALLAS PARKWAY
SUITE 620
DALLAS, TX 75254
EXAMINER
BERMUDEZ LOZADA, ALFREDO
ART UNIT PAPER NUMBER
2825
NOTIFICATION DATE DELIVERY MODE
02/12/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docket@pj-iplaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte HAIYAN GONG, LEI WANG, SING-RONG LI,
HWONG-KWO LIN, and PAI-YI CHANG
____________

Appeal 2019-003692
Application 14/160,706
Technology Center 2800
____________

Before CATHERINE Q. TIMM, MONTÉ T. SQUIRE, and
MERRELL C. CASHION, JR., Administrative Patent Judges.

CASHION, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
Final Rejection of claims 1–20. We have jurisdiction under 35 U.S.C.
§ 6(b).
We AFFIRM IN PART.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies NVIDIA Corporation as the real party
in interest. Appeal Br. 3.
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The invention is directed to a negative bit line write assist system
(apparatus) and a negative bit line write assist method. Spec. ¶ 1. Claim 1
illustrates the invention:
1. A negative bit line write assist system, comprising:
an array voltage supply;
a static random access memory (SRAM) cell that is
coupled to the array voltage supply and controlled by bit lines
during a write operation; and
a bit line voltage unit that is coupled to the SRAM cell,
wherein:
a distributed capacitance is controlled by a single
write assist command to provide generation of a negative
bit line voltage during the write operation,
said bit line voltage unit including a write assist
grounding switch and write assist buffer circuit,
said single write assist command applied to said
write assist buffer circuit to provide a charging voltage to
said distributed capacitance,
said single write assist command also applied to
said write assist grounding switch, and
said distributed capacitance is a fringing
capacitance in an upper metal layer of an array of said
SRAM cells.
Independent claim 11 is directed to a negative bit line write assist
method using essentially the negative bit line write assist system of claim 1.
Appellant (Appeal Br. 4–5) requests review of the following
rejections from the Examiner’s Final Office Action:
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I. Claims 2–6 and 12–16 rejected under 35 U.S.C. § 112(b) as
indefinite for failing to particularly point out and distinctly claim the subject
matter which the inventor or a joint inventor regards as the invention.

II. Claims 1–20 rejected under 35 U.S.C. § 103 as unpatentable
over Wu (US 8,174,867 B2, issued May 8, 2012) and Turner (US
2004/0233701 A1, published November 25, 2004).

OPINION
After review of the positions the Appellant provides in the Appeal and
Reply Briefs and the Examiner provides in the Final Action and the Answer,
we AFFIRM the Examiner’s rejection of claims 2–6 and 12–16 rejected
under 35 U.S.C. § 112(b) for the reasons the Examiner presents, but
REVERSE the Examiner’s prior art rejection of claims 1–20 under 35
U.S.C. § 103 for the reasons Appellant presents. We add the following for
emphasis.

REJECTION UNDER § 112(b) - Indefiniteness
The text of 35 U.S.C. § 112 (b) requires “[t]he specification shall
conclude with one or more claims particularly pointing out and distinctly
claiming the subject matter which the inventor or a joint inventor regards as
the invention.” “As the statutory language of ‘particular[ity]’ and
‘distinct[ness]’ indicates, claims are required to be cast in clear—as opposed
to ambiguous, vague, indefinite—terms.” In re Packard, 751 F.3d 1307,
1313 (Fed. Cir. 2014). Thus, the test for determining the question of
indefiniteness may be formulated as whether the claims “set out and
circumscribe a particular area with a reasonable degree of precision and
particularity.” In re Moore, 439 F.2d 1232, 1235 (CCPA 1971). With
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regard to the reasonableness standard, one must consider the language in the
context of the circumstances. Packard, 751 F.3d at 1313. Language is an
imprecise method of drawing boundaries delineating patent rights, thus
unreasonable precision cannot be demanded. Id. On the other hand, the
claims must notify the public of what they are excluded from making and
using. Id. For this reason, while exact precision is not required, an applicant
is required to use language as precise as the subject matter reasonably
permits. Id.
We first note that the Examiner rejects claims 6 and 16 as indefinite
because the claims recite the language “wherein the distributed capacitance
includes a fringing capacitance.” Final Act. 3. According to the Examiner,
the noted recitation of the claims is redundant because independent claims 1
and 11 already recite it. Id. Appellant does not present any arguments
addressing the rejection of these claims. See generally Appeal Br. and
Reply Br.; Ans. 3–4. Accordingly, we summarily affirm the rejection of
these claims.
The Examiner additionally rejects claims 2 and 12 as indefinite
because the claims recite that the “distributed capacitance includes an upper
metal coupling capacitance.” Final Act. 2. According to the Examiner,
independent claims 1 and 11 recite that the distributed capacitance is a
fringing capacitance in an upper metal layer. Id. at 2–3. The Examiner
contends that one skilled in the art would be unable to ascertain the scope of
these claims because it is not clear whether the distributed capacitance is
generated from an upper metal coupling or it is limited to just fringing
capacitances. Id. at 3.
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Appellant argues that claims 2 and 12 recite that the claimed
distributed capacitance includes both, the fringing capacitance of claims 1
and 11 as well as an upper metal coupling capacitance. Appeal Br. 5. That
is, Appellant argues that claims 2 and 12 include the fringing capacitance
and an additional upper metal coupling capacitance other than a fringing
capacitance.
Appellant’s argument does not identify error in the Examiner’s
determination of indefiniteness.
As the Examiner notes, the independent claims recite that the
distributed capacitance is the fringing capacitance. Ans. 7. In fact, the
Specification discloses that the “distributed capacitances are typically
fringing capacitances in an upper metal layer of the SRAM array or
memory.” Spec ¶ 21. Thus, the Specification only identifies fringing
capacitances as being distributed capacitances. There is no disclosure of
what capacitances other than fringing capacitances could be distributed
capacitances. Therefore, we agree with the Examiner that the language of
the independent claims limits the distributed capacitance to just the fringing
capacitance. Id. While Appellant asserts that dependent claims 2 and 12
includes an additional upper metal coupling capacitance, Appellant does not
direct us to any portion of the Specification or provide an adequate
explanation in support of this assertion. See generally Appeal Br. Thus, the
claim language, when read in light of the written description, is confusing.
In re Cohn, 438 F.2d 989, 1001 (CCPA 1971) (holding claims indefinite
based on an inconsistency in meaning when the claim is read in light of the
disclosure).
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Moreover, the language of the independent claims recites that the
“distributed capacitance is a fringing capacitance in an upper metal layer of
an array of [] SRAM cells.” Thus, the fringe capacitance would meet
dependent claims 2 and 12 recitation of a “distributed capacitance [that]
includes an upper metal coupling capacitance.” This raises the same issue
that the Examiner pointed out with respect to claims 6 and 16, namely, that
claims 2 and 12 do not further limit the subject matter of independent claims
1 and 11.
Accordingly, on this record, claims 2–6 and 12–16 are indefinite for
the reasons the Examiner presents and we give above.

REJECTION UNDER § 103
After review of the respective positions the Appellant presents in the
Appeal and Reply Briefs and the Examiner presents in the Final Action and
the Answer, we REVERSE for the reasons the Appellant provides. We add
the following for emphasis.
Claim 12
Independent claim 1 recites a single write assist command to (1)
control a distributed capacitance, (2) to be applied to a write assist buffer
circuit to provide a charging voltage to said distributed capacitance, and (3)
to also be applied to a write assist grounding switch.
We refer to the Examiner’s Final Office Action and the Answer for a
complete statement of the rejection of claim 1. Final Act. 4–5; Ans. 9–10.

2 Independent claim 11 also recites a single write assist command.
Accordingly, we limit our discussion to independent claim 1 with the
understanding that our discussion applies equally to independent claim 11.
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Briefly, the Examiner finds that Wu3 shows that input signals to
sources SC1 and SC2 are used together to control the negative voltage
generation circuit to improve the write operation (write-assist). Final Act. 4;
Ans. 9–10. While the Examiner acknowledges that SC1 and SC2 are distinct
signals, the Examiner contends that these signals used together represent a
“single write assist command,” as claimed. Final Act. 4; Ans. 10.
Appellant argues that Wu teaches sources SC1 and SC2 are controlled
by distinctly different command signals and not by a single command signal.
Appeal Br. 7; see Wu Figure 3 (showing different input signals (command
signals) for sources SC1 and SC2). Appellant contends that Wu teaches an
input signal to signal source SC1 that controls (through invertor INV1 and
transistors P1 and N1) either charging or discharging (through NMOS
transistor N2) capacitor CAP. Appeal Br. 7 (citing Wu col. 3, l. 66–col. 4, l.
9). Appellant further contends that Wu teaches using a different input signal
to signal source SC2 to control supply voltage regulator 40 which regulates a
high supply voltage HV between node IN2 and SUPP and can vary
dependent on power supply voltage VDD. Appeal Br. 7–8 (Wu col. 4, ll.
39–62). Thus, Appellant asserts that Wu’s input signals to signal sources
SC1 and SC2 are distinctly different command signals controlling distinctly
different functions and, as a result, Wu does not teach that SC1 and SC2 are
a single command controlling source as the Office Action purports. Appeal
Br. 8.

3 A discussion of the reference to Turner is unnecessary for disposition of
this rejection. The Examiner relied on Turner for its teaching of fringe
capacitances and not to address the claimed single write assist command.
See Final Act. 4–5.
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We agree with Appellant that there is reversible error in the
Examiner’s determination of obviousness.
The Examiner bears the initial burden of presenting a prima facie case
of obviousness. In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992).
“[R]ejections on obviousness grounds cannot be sustained by mere
conclusory statements; instead, there must be some articulated reasoning
with some rational underpinning to support the legal conclusion of
obviousness.” In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006), quoted with
approval in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
The Examiner’s assertion that Wu’s two different input signal to
sources SC1 and SC2 represent a “single write assist command,” as claimed
(Final Act. 4; Ans. 10), is unsupported by a preponderance of the evidence.
As Appellant argues, the input signals to sources SC1 and SC2 are distinctly
different command signals controlling distinctly different functions. Appeal
Br. 8. While these input signals may play a role in improving the write
operation, the Examiner directs us to no portion of Wu that identifies the
signals themselves as write assist commands, whether taken alone or
combined. Nor does the Examiner adequately explain why one skilled in the
art would have inferred that Wu’s distinct input signals would represent a
single write assist command.
If there is any single write assist command generated by Wu, this
command would be the output of Wu’s negative-voltage generator 26
(designated by the Examiner as corresponding to the claimed bit line voltage
unit (Final Act. 4)). See Wu Figure 3. In such a case, this output is at least
not applied to a write assist buffer circuit to provide a charging voltage to
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said distributed capacitance or to a write assist grounding switch, as required
by the subject matter of claim 1.
Thus, the Examiner has not provided an adequate technical
explanation with the requisite rational underpinning of why or how one
skilled in the art would have arrived at the claimed single write assist
command from Wu’s teachings. The Examiner has not made a prima facie
case of obviousness.
Accordingly, we reverse the Examiner’s prior art rejection of claims
1–20 under 35 U.S.C. § 103 for the reasons the Appellant present and those
we provide above.
CONCLUSION
Because the affirmed rejection does not reach all the claims, our
decision is an affirmance in part.
In summary:

Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
2–6, 12–16 112(b) Indefiniteness 2–6, 12–16
1–20 103 Wu 867, Turner 1–20
Overall
Outcome
2–6, 12–16 1, 7–11,
17–20

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).

AFFIRMED IN PART