Gabriel Tarasuk-Levin et al.

Patent Trials and Appeals Board

Dec 26, 2019

14752635 - (D) (P.T.A.B. Dec. 26, 2019)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/752,635 06/26/2015 Gabriel TARASUK-LEVIN C086 3046
136237 7590 12/26/2019
Barta, Jones & Foley, P.C.
(Patent Group - VMware)
2805 Dallas Parkway
Suite 222
Plano, TX 75093
EXAMINER
HAILU, TESHOME
ART UNIT PAPER NUMBER
2434
NOTIFICATION DATE DELIVERY MODE
12/26/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docket@bjfip.com
ipadmin@vmware.com
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte GABRIEL TARASUK-LEVIN and REILLY GRANT
Appeal 2018-007820
Application 14/752,635
Technology Center 2400
Before MAHSHID D. SAADAT, DENISE M. POTHIER, and
CATHERINE SHIANG, Administrative Patent Judges.
POTHIER, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1,2 appeals from the
Examiner’s decision to reject claims 1–20. Appeal Br. 3. We have
jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as VMware, Inc.
Appeal Br. 1.
2 Throughout this opinion, we refer to the Non-Final Action (Non-Final
Act.) mailed September 7, 2017, the Appeal Brief (Appeal Br.) filed March
5, 2018, the Examiner’s Answer (Ans.) mailed May 25, 2018, and the Reply
Brief (Reply Br.) filed July 23, 2018.
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Application 14/752,635

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CLAIMED SUBJECT MATTER
The Specification describes live migration programs for migrating a
memory state of a source host computer to a destination host computer.
Spec. ¶ 1. The Specification indicates receiving the memory state consumes
bandwidth and resources and can act as a bottleneck. Id. Encryption (e.g.,
end-to-end encryption used by government) also increases the bandwidth
and resources consumed and can impact live migration performance. Id. ¶ 5.
The claims are directed to “enabl[ing] rapid encrypted live migration of
virtual machines (VMs) using asynchronous encryption and decryption.” Id.
¶ 6. Illustrative claim 1 is reproduced below:
A system comprising:
a memory area associated with a computing device, said
memory area storing memory blocks; and
a processor programmed to:
encrypt, at a first host, one or more memory blocks
associated with a source virtual machine (VM);
transfer the one or more encrypted memory blocks to one
or more second hosts; and
decrypt, at the one or more second hosts, only those
memory blocks of the one or more encrypted memory blocks
needed to execute a destination VM at the one or more second
hosts.

Appeal Br. A-1 (Claims App.) (emphasis added).
REFERENCES
The prior art relied upon by the Examiner is:
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Application 14/752,635

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Name Reference Date
Feldman US 2004/0047466 A1 Mar. 11, 2004
Nam US 2004/0247295 A1 Dec. 9, 2004
Factor US 2007/0168284 A1 July 19, 2007
Spohrer US 2008/0065902 A1 Mar. 13, 2008
Patel US 2008/0137837 A1 June 12, 2008
Kaabouch US 2010/0064144 Al Mar. 11, 2010
Lee US 2010/0281273 A1 Nov. 4, 2010
Tsirkin US 2015/0212839 Al July 30, 2015 (filed
Jan. 28, 2014)

OBVIOUSNESS REJECTION BASED ON TSIRKIN AND KAABOUCH
Claims 1, 2, 9, 11–13, 15–17, and 20 are rejected under 35 U.S.C.
§ 103 as being unpatentable over Tsirkin and Kaabouch. Non-Final Act.
3–8. The Examiner cites to Tsirkin to teach all limitations in claim 1 (id. at
3–4 (citing Tsirkin ¶¶ 8, 24, 35, Fig. 1)), except for a processor programmed
to decrypt “only those memory blocks of the one or more encrypted memory
blocks needed for execution.” Id. at 4. The Examiner turns to Kaabouch in
combination with Tsirkin to teach this missing feature. Id. at 4–5 (citing
Kaabouch ¶¶ 13–14).
Appellant asserts “no combination of Tsirkin and Kaabouch describes
or suggests ‘decrypt, at the one or more second hosts, only those memory
blocks of the one or more encrypted memory blocks needed to execute a
destination VM at the one or more second hosts,’ as recited in claim 1.”
Appeal Br. 8. Specifically, Appellant states Tsirkin relates to excluding
redundant transformation of memory pages on a running virtual machine on
host B that is attempting to access a memory page. Id. at 9. Appellant
further asserts Kaabouch does not describe decrypting “only those memory
blocks of the one or more encrypted memory blocks that are needed to
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Application 14/752,635

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execute a destination VM at the host” as claim 1 recites. See id. at 10; see
Reply Br. 4.

ISSUE
Under § 103, has the Examiner erred by determining that Tsirkin and
Kaabouch collectively would have taught or suggested “a processor
programmed to . . . decrypt, at the one or more second hosts, only those
memory blocks of the one or more encrypted memory blocks needed to
execute a destination VM at the one or more second hosts”?

ANALYSIS
On the record before us, Appellant has persuaded us the Examiner has
erred. The Examiner states Tsirkin teaches “decrypt[ing], at the one or more
second hosts, the one or more encrypted memory blocks to execute a
destination VM at the one or more second host.” Non-Final Act. 4 (citing
Tsirkin ¶ 35). Tsirkin teaches a live migration of the virtual machine
execution state from an origin host to a destination host (e.g., from host A to
host B in Figure 1), including transmitting the encrypted virtual machine
execution state as memory blocks to a destination host (e.g., host B). Tsirkin
¶ 24. Tsirkin further teaches reverse transforming (e.g., decrypting) “the
memory block.” Id. ¶ 35 (emphasis added). When viewing this cited
passage in the context of Tsirkin as a whole, Tsirkin teaches reverse
transforming “the transformed memory block corresponding to the memory
page being accessed [by the virtual machine].” Id. ¶ 34.
Because Tsirkin’s virtual machine at the destination (e.g., a
destination VM) is attempting to access a virtual machine’s memory page,
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the noted passages (id. ¶¶ 6, 34–35, Fig. 3) suggest the virtual machine at the
destination (e.g., a destination VM) has been executed as Appellant indicates
(see Appeal Br. 9–10) and thus does not teach decrypting “those memory
blocks . . . needed to execute a destination VM at the one or more second
hosts” as claim 1 recites. On the record, the Examiner fails sufficiently to
explain how decrypting the memory block corresponding to a virtual
machine memory page being accessed in Tsirkin corresponds to decrypting
memory blocks “needed to execute a destination VM” at the second host as
claim 1 recites. See Ans. 15–16 (repeating that Tsirkin teaches reverse
transforming the memory block and focusing on Kaabouch); Reply Br. 4
(stating “the Examiner omits the part of the claimed invention that is
directed to decrypting only those memory blocks [that are] needed to
execute a destination VM at the one or more second hosts.”). The record
also does not explain clearly how the memory block comprising or
corresponding to one or more virtual machine memory page in Tsirkin (see
Tsirkin ¶¶ 32, 34) is a block needed to execute a destination VM.
Additionally, to the extent Kaabouch is cited to teach or suggest the
above-noted feature missing from Tsirkin, including those related memory
blocks needed to execute a destination VM as claim 1 requires (see Non-
Final Act. 4–5 (citing Kaabouch ¶¶ 13–14)), we agree with Appellant that
Kaabouch fails to teach or suggest what is missing. Appeal Br. 10–11;
Reply Br. 4.
The Examiner states that Kaabouch teaches “[t]he data needed for
execution in Kaabouch is inside the memory block and according to
Kaabouch, when the data is needed for execution, only the memory block
containing that data is decrypted.” Ans. 16. Kaabouch teaches retrieving
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“the memory block containing the [requested] data and pass[ing] the
memory block to the decryption engine” for decryption, storage, and
retrieval. Kaabouch ¶ 14. Although this passage teaches decrypting a
memory block that contains the requested data, this passage as well as cited
paragraph 13 do not teach or suggest decrypting memory blocks needed to
execute data (e.g., perform an instruction), let alone decrypting “only those
memory blocks . . . needed to execute a destination VM” (emphasis added)
as claim 1 requires. For this reason and given the present record, we agree
with Appellant that Kaabouch does not teach or suggest “the feature of
‘blocks needed to execute a destination VM at the one or more second
hosts[,]’ . . . in claim 1.” Reply Br. 4.
Independent claims 9 differs in scope from claim 1, such as claiming
“decrypting only those memory blocks of the one or more encrypted
memory blocks that are required to perform a checkpoint restore operation
of a source virtual machine at the one or more destination hosts” (Appeal
Br. A-2 (Claims App.) (emphasis added)) instead of “decrypt[ing], at the one
or more second hosts, only those memory blocks of the one or more
encrypted memory blocks needed to execute a destination VM at the one or
more second hosts” (id. at A-1 (Claims App.)). Independent claim 17 is
commensurate in scope with claim 9. Compare id. at A-4 (Claims App.),
with id. at A-2 (Claims App.). The Examiner relies on the same passages in
Tsirkin and Kaabouch to teach or suggest the recitations in claims 9 and 17.
Non-Final Act. 5 (stating “[c]laims 9 and 17 are rejected under the same
reason set forth in rejection of claim 1”). For reasons similar to those
previously indicated, the Examiner has not explained sufficiently how the
passages Tsirkin and Kaabouch, alone or in combination, relied upon in the
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rejection (id. at 3–5; see Ans. 15–16) teach or suggest “decrypting only those
memory blocks of the one or more encrypted memory blocks that are
required to perform a checkpoint restore operation of a source virtual
machine at the one or more destination hosts” as claims 9 and 17 similarly
recite. Id. at A-2, A-4 (Claims App.) (emphasis added).
For the foregoing reasons, Appellant has persuaded us of error in the
rejection of (1) independent claim 1, 9 and 17 and (2) dependent claims 2–8,
10–16, and 18–20 for similar reasons.
THE REMAINING OBVIOUSNESS REJECTIONS
Claims 3–8, 14, 18, and 19 are rejected under 35 U.S.C. 103 as being
unpatentable over Tsirkin, Kaabouch, and one additional reference (e.g.,
Feldman, Spohrer, Nam, Factor, Patel, and Lee). Non-Final Act. 8–14. The
Examiner has not relied upon the additional references to teach or suggest
the above-identified limitation in claims 1, 9, and 17 missing from Tsirkin
and Kaabouch. See id. Accordingly, for reasons similar to those above for
independent claims 1, 9, and 17 and because each of the rejected claims
ultimately depends from one of claims 1, 9, and 17, we do not sustain the
remaining rejections.
DECISION SUMMARY
In summary:
Claims
Rejected
35
U.S.C. §
References Affirmed Reversed
1, 2, 9, 11–13,
15–17, 20
103 Tsirkin,
Kaabouch
1, 2, 9, 11–13,
15–17, 20
3, 14, 18 103 Tsirkin,
Kaabouch,
Feldman
3, 14, 18
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Application 14/752,635

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4 103 Tsirkin,
Kaabouch,
Spohrer
4
5, 10, 19 103 Tsirkin,
Kaabouch, Nam
5, 10, 19
6 103 Tsirkin,
Kaabouch, Factor
6
7 103 Tsirkin,
Kaabouch, Patel
7
8 103 Tsirkin,
Kaabouch, Lee
8
Overall
Outcome
1–20

REVERSED