FREESCALE SEMICONDUCTOR INC.

Patent Trials and Appeals Board

Apr 2, 2021

2020000216 (P.T.A.B. Apr. 2, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/943,613 11/17/2015 CRISTIAN CORNELIU TOMESCU AM21348ES (038.0667) 6428
50996 7590 04/02/2021
NXP (FS) - LKGlobal
6501 William Cannon Drive West
Austin, TX 78735
EXAMINER
WANG, JIN CHENG
ART UNIT PAPER NUMBER
2613
NOTIFICATION DATE DELIVERY MODE
04/02/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
ip.department.us@nxp.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte CRISTIAN CORNELIU TOMESCU and DRAGOS PAPAVA
Appeal 2020-000216
Application 14/943,613
Technology Center 2600
BEFORE MAHSHID D. SAADAT, JUSTIN BUSCH, and
JENNIFER L. McKEOWN, Administrative Patent Judges.
MCKEOWN, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1 and 4–20.2 We have jurisdiction
under 35 U.S.C. § 6(b).
We AFFIRM IN PART.

1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as NXP USA, Inc.
Appeal Br. 2.
2 Appellant asserts they do not appeal the rejections of claims 14–20.
Appeal Br. 4. These claims, though, have not been cancelled and, thus,
claims 14–20, and rejections thereof, are pending before us.
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CLAIMED SUBJECT MATTER
The claims are directed to “graphical processing, and more
specifically relate to graphical layer blending.” Spec. 2.
Claim 1, reproduced below, is illustrative of the claimed subject
matter:
1. A processing unit, comprising:
a first display control unit, wherein the first display control
unit is configured to receive a first plurality of graphical layers
and blend the first plurality of graphical layers to generate a first
composed image for each blending cycle of the first display
control unit, the first display control unit including a first display
interface;
a memory unit, the memory unit coupled to the first
display control unit and configured to receive and store the first
composed image, wherein the memory unit includes a first
memory buffer and a second memory buffer, and wherein the
first display control unit is configured to switch between writing
the first composed image to the first memory buffer and writing
the first composed image to the second memory buffer; and
a second display control unit, wherein the second display
control unit is coupled to the memory unit and is configured to
receive a second plurality of graphical layers and the first
composed image and blend the second plurality of graphical
layers and the first composed image to generate a final composed
image, the second display control unit including a second display
interface, and wherein the second display control unit is
configured to switch between receiving the first composed image
from the first memory buffer and receiving the first composed
image from the second memory buffer to facilitate real time
generation of the final composed image for each blending cycle
of the second display control unit.

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REFERENCES
The prior art relied upon by the Examiner is:
Name Reference Date
Blossom US 5,546,518 Aug. 13, 1996
Frensch US 2007/0002072 A1 Jan. 4, 2007
Naito US 2010/0045691 A1 Feb. 25, 2010
Morino US 2012/0036418 A1 Feb. 9, 2012
Staudenmaier US 2015/0109330 A1 Apr. 23, 2015

REJECTIONS
The Examiner rejected claims 1, 4, 7, 9–12, 14, 18, and 20 under
35 U.S.C. § 103 as unpatentable over Staudenmaier and Naito. Final Act.
16, 24, 28, 30, 41, 43, 52.
The Examiner rejected claims 5, 6, 13, and 15–17 under 35 U.S.C.
§ 103 as unpatentable over Staudenmaier, Naito, and Frensch. Final Act. 26,
42, 49.
The Examiner rejected claims 8 and 19 under 35 U.S.C. § 103 as
unpatentable over Staudenmaier, Naito, Frensch, Morino, and Blossom.
Final Act. 52.
OPINION
THE OBVIOUSNESS REJECTION BASED ON STAUDENMAIER AND NAITO
Claims 1, 4, 7, 9, 10, 12, 14, 18, and 20
Appellant argues that Staudenmaier fails to teach or suggest the
claimed first display control unit and second display control unit. Appeal
Br. 16. In particular, Appellant contends that blenders 31, 32, and 33 in
Staudenmaier are not distinct display control units, rather these blenders are
all part of the same display controller. Appeal Br. 17. According to
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Appellant, “The blenders 31, 32, 33 are thus parts of the same blending
stage 11, which is itself described as only being part of a larger display
controller.” Appeal Br. 17 (citing Staudenmaier ¶¶ 10, 16, and 17).
Appellant also points out that each of blenders 31, 32, and 33 do not receive
a plurality of graphical layers and do not each have its own display interface,
as required by the claims. Appeal Br. 17. As such, Appellant asserts that
Staudenmaier’s blenders do not satisfy the limitations of the claimed first
and second display control units. Appeal Br. 17.
Appellant also argues that Staudenmaier fails to teach or suggest the
claimed memory unit. According to Appellant, Staudenmaier’s offline
memory does not receive and store a first composed image from a first
display control unit and does not provide the first composed image to a
second display control unit. Appeal Br. 18.
We find Appellant’s arguments unpersuasive. Staudenmaier, like the
claimed invention, describes a blending stage to construct “more complex
output images” by using an offline blending memory. Staudenmaier ¶ 18.
Staudenmaier further explains that, by using the offline memory, “[t]he
maximum complexity of the output graphic content is not limited by the
amount of input channels” such that “[w]ith, e.g., four input channels, five
six or even more layers can be blended into one output image, without
needing additional blenders or input channels.” Staudenmaier ¶ 18.
As the Examiner explains, the Specification does not expressly define
a first and second display control unit, but rather generally describes each of
the first and second display control unit as blending circuits. Ans. 39; see
also, e.g., Spec. ¶¶ 14, 19 (describing that first and second control circuits
are configured to each receive and blend a plurality of graphical layers).
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The Examiner determines that Staudenmaier’s blenders, like the claimed
display control units, receive and blend a plurality of graphical layers. For
example, annotated Staudenmaier’s Figure 2 depicted below, identifies a
first and second display control unit as required by the claims.

Annotated Figure 2 of Staudenmaier depicting blenders 31, 32, and 33
and offline blending memory
Specifically, blender 31, i.e. first display control unit, receives input
channels 21 and 22, i.e. plurality of graphical layers, and performs blending
tasks to combine the layers into a blended image. Staudenmaier ¶¶ 16–17,
Fig. 2. In one embodiment, Staudenmaier stores the outputted offline
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blending results, i.e. first composed image, in the offline blending memory
15, i.e. memory unit. Staudenmaier ¶¶ 17–18. Collectively, blenders 32 and
33, i.e. second control display unit, receive input channels 23 and 24, i.e.
plurality of graphical layers, and receive the outputted offline blending
results, i.e. first composed image, from the offline blending memory, i.e.
memory unit. Blenders 32 and 33 then blend or combine the layers and
offline blending results into a blended image to generate output image 25.
Staudenmaier ¶¶ 16–18. As such, Staudenmaier teaches a first and second
display control unit that each receive a plurality of graphical layers and
blend them to generate an image, as required by the claim. See also Ans. 4
(noting “Staudenmaier’s first control unit and the second control unit are
arranged/drawn in the same manner as appellants’ FIG. 2.”).
Staudenmaier does not teach the claimed first or second buffer or
switching writing or reading between the buffers. Naito, however, teaches
this limitation. See, e.g., Final Act. 20–21; Ans. 6–7. For example, Naito
generally teaches a first frame buffer 303 and second frame buffer 304 with
buffer switching means 15 that switches from one buffer to the other. Naito
Fig. 8, ¶¶ 88, 95. Moreover, as the Examiner also explains, including a
memory switch module would have been well known in the graphical
processing art at the time of the invention. Ans. 35. To arrive at the claimed
invention, the Examiner modifies Staudenmaier’s offline memory unit to
include a first and second buffer and switching module, as taught by Naito.
Appellant fails to persuasively identify error in this combination.3

3 We note that Appellant also argues that Naito fails to teach or suggest the
first and second display control units. See, e.g., Appeal Br. 22–23; Reply
Br. 5–7. Because we determine that Staudenmaier teaches the claimed first
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Appellant also argues
each of [Staudenmaier’s] blenders 31, 32, and 33 does not have
its own display interface as the display controllers of claim 1 are
recited as including, and instead the blending stage 11 outputs to
a display only through the final blender 33. Thus, there is not a
“first display interface” of a “first display control unit” even if
the output if blender 33 is considered to be the “second display
interface.”
Reply Br. 5.
We disagree. Staudenmaier, like the described invention, outputs a
blended image to a display interface. See, e.g., Staudenmaier Fig. 2.
Notably, neither the Specification nor the original claims describe a first
interface display unit. Instead, the Specification only generally describes a
display interface. The Specification describes that “step 310 is to output the
final composed image [f]or example, by outputting the final composed
image through a display interface to an associated LCD display.” Spec. ¶ 27.
The Specification also states that “the second display control unit [is] further
configured to output the second composed images to a display interface.”
Spec. ¶ 30. Appellant’s summary of claim 1 does not include a first display
interface or any identified support for this limitation. See Appeal Br. 6–7
(summarizing the invention of claim 1 and identifying support in the
Specification, but not including a first display interface limitation). Reading
the claims in light of the Specification, we construe the first display interface
to merely require a connection for outputting the blended result from the
first display control unit. As such, based on the record before us, we are not

and second display control units, we need not address these arguments with
respect to Naito.
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persuaded that Staudenmaier fails to teach or suggest the first display
interface limitation.
In the Reply Brief, Appellant argues that “simply replacing the
memory unit in Staudenmaier with the memory unit in Naito” would not
meet the claimed limitations. Reply Br. 9. In particular, Appellant argues
that Staudenmaier fails to teach or suggest the first and second display
control units and Naito fails to teach the claimed “memory unit configured
to be written to by one display control unit and read by another display
control unit.” Reply Br. 9–10.
We disagree. As discussed above, we determine that Staudenmaier
teaches the claimed first and second display units and the memory unit while
Naito teaches the claimed first and second memory buffers. Together, then,
the combination of Staudenmaier teaches the claimed invention. Moreover,
as the Examiner explains, a skilled artisan would have modified
Staudenmaier’s offline blending memory of FIG. 2 in view of “Naito’s
memory unit having two display buffers and memory switch module in
Naito FIG. 8 to switch between the two memory buffers in replacement of
Staudenmaier’s single memory unit and single memory switch module.”
Ans. 4. The Examiner further explains “[t]he combination is proper because
it is advantageous to have utilized one of first composed images stored from
one of the memory buffers.” Ans. 4. As such, Appellant’s arguments are
unpersuasive.

Claim 11
With respect to claim 11, Appellant additionally argues that Naito
fails to teach or suggest the claimed EndOfBlending flag. Appeal Br. 24.
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Appellant points out that “the EndOfBlending flag is provided to
synchronize the blending of the two display control units” or, essentially, to
“facilitate[] real time blending of all the graphical layers with the two
display control units.” Appeal Br. 27. According to Appellant,
nothing in these cited portions of Naito describe[s] the setting of
any flag “to indicate completion of the first composed image”
(emphasis added). . . . Instead, appellants submit that the “pointer
information” cited in paragraph 0088 is an indication of location
of the image in memory, and not a flag that is set to indicate
when completion of a graphical layer blending by a first display
control unit has occurred or otherwise cause a start of additional
blending in a second display control unit.
Appeal Br. 27. Additionally, Appellant contends that Naito’s vertical
synchronization signal is also distinct from the claimed EndOfBlending flag.
Appeal Br. 28. Specifically, Appellant argues:
Naito clearly states in paragraph 0056 that the “vertical
synchronization signal” is output to the frame buffer “at the
timing at which vertical synchronization occurs”. Furthermore,
nothing in Naito suggests that this vertical synchronization
occurs at a time when the first composed image is complete.
Note also that paragraph 0057 of Naito clearly states that this
synchronization is done to prevent flicker, and is not described
as being used to facilitate the combing with additional graphical
layers.
Appeal Br. 28.
We are persuaded of error in the Examiner’s rejection of claim 11.
The Specification describes the EndOfBlending flag, in one embodiment:
the first display control unit 202 can be implemented to raise a
first interrupt and set an EndOfBlending flag when the blending
of the first composed image is completed. Likewise, the second
display control unit 206 can be implemented to raise a second
interrupt when the final composed image is displayed.
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. . . when the EndOfBlending flag has been set the first and
second memory buffers are switched, and a new blending cycle
is started for both the first display control unit 202 and the second
display control unit 204. However, if the first display control unit
202 has not finished blending its new composed image the
EndOfBlending flag is not set and the second display control unit
204 will start a new blending cycle using the previous composed
image while the first display control unit 202 continues to blend
a new image. Thus, the first display control 202 and the second
display control unit 204 can blend independently while using the
EndOfBlending flag to synchronize activities and ensure that the
second display control unit 204 uses the correct image data from
the first display control unit 202.
Spec. ¶¶ 22–23.
Naito, in contrast, teaches transmitting a pointer to the drawing order
control means to identify the location of the stored image. Naito ¶¶ 87–88.
Naito also, as Appellant points out, teaches a vertical synchronization signal
to prevent flicker. Naito ¶¶ 94–95. Based on the record before us, the
Examiner has not sufficiently shown how Naito’s memory pointer or vertical
synchronization signal satisfies the claimed EndOfBlending flag limitation.
Accordingly, we affirm the rejection of claims 1, 4, 7, 9, 10, 14, 18,
and 20 as unpatentable over Staudenmaier and Naito, but we reverse the
rejection of claims 11 and 12.

THE OBVIOUSNESS REJECTION BASED ON STAUDENMAIER, NAITO, AND
FRENSCH
Claims 5, 6, 13, and 15–17
With respect to claims 5 and 6, Appellant additionally argues that
Frensch fails to teach or suggest the claimed buffer switch module. Appeal
Br. 29–30. Specifically, Appellant maintains that Frensch’s selector controls
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where image layers are stored prior to blending and, thus, fails to satisfy the
claimed buffer switch module. Id.
Claims 5 and 6 recite:
5. The processing unit of claim 1, further comprising a
buffer switch module, where the first display control unit is
configured to selectively write the first composed image to either
the first memory buffer or the second memory buffer as selected
by the buffer switch module, and where the second display
control unit is configured to selective read the first composed
image from either the first memory buffer or the second memory
buffer as selected by buffer switch module.

6. The processing unit of claim 5, wherein the buffer
switch module alternates the writing of the first composed image
between the first memory buffer and the second memory buffer,
and wherein the buffer switch module alternates in opposite
fashion the reading of the first composed image between the
second memory buffer and the first memory buffer.
Claims App’x.
Notably, claim 1 recites that the first display control unit alternates
writing a first composed image in the first and second buffers and the second
display control unit alternates receiving the first composed image from the
first and second buffers. Claim 5, depending from claim 1, merely adds a
buffer switch module to select which buffer the display control units write to
and read from. Frensch teaches a selector to identify where, between two
memories, to store the pixel data. Final Act. 27. In other words, Frensch at
least suggests to a skilled artisan a component to select which location to
store data and then receive the data like the claimed buffer switch module.
As such, we are not persuaded of error in the rejection of claims 5 and 6.
Appellant does not present separate arguments of patentability for
claims 13 and 15–17. As discussed above though, we are persuaded of error
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in the rejection of claim 11. As such, we are not persuaded of error in the
rejections of claims 15–17, which depend from claim 14, but are persuaded
of error in the rejection of claim 13, which depends from claim 11.
Accordingly, we affirm the rejection of claims 5, 6, and 15–17 as
unpatentable over Staudenmaier, Naito, and Frensch, but we reverse the
rejection of claim 13.

THE OBVIOUSNESS REJECTION BASED ON STAUDENMAIER, NAITO, FRENSCH,
MORINO, AND BLOSSOM
Claims 8 and 19
Appellant does not present separate arguments of patentability for
claims 8 and 19. Instead, Appellant relies on the arguments presented for
claim 1. Appeal Br. 20. As discussed above, we find these arguments
unpersuasive. Accordingly, we affirm the rejection of claims 8 and 19 as
unpatentable over Staudenmaier, Naito, Frensch, Morino, and Blossom.
CONCLUSION
The Examiner’s rejections of claims 1, 4–10, and 14–20 are affirmed,
but the rejection of claims 11–13 is reversed.

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DECISION SUMMARY
In summary:
Claim(s)
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1, 4, 7, 9,
10, 11, 12,
14, 18, 20
103 Staudenmaier,
Naito
1, 4, 7, 9,
10, 14, 18,
20
11, 12
5, 6, 13, 15–
17
103 Staudenmaier,
Naito, Frensch
5, 6, 15–17 13
8, 19 103 Staudenmaier,
Naito, Frensch,
Morino, Blossom
8, 19
Overall
Outcome
1, 4–10, 14–
20
11–13
TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv).
AFFIRMED IN PART