11509178 (P.T.A.B. Jul. 29, 2013)

Ex Parte Zulauf

Patent Trial and Appeal BoardJul 29, 2013

11509178 (P.T.A.B. Jul. 29, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 11/509,178 08/24/2006 John M. Zulauf 1458-P0052 4564 89320 7590 07/30/2013 Polansky & Associates, P.L.L.C. 12117 FM 2244 3-160 Austin, TX 78738 EXAMINER DOAN, DUC T ART UNIT PAPER NUMBER 2185 MAIL DATE DELIVERY MODE 07/30/2013 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________________ Ex parte JOHN M. ZULAUF ____________________ Appeal 2011-000279 Application 11/509,178 Technology Center 2100 ____________________ Before JOSEPH F. RUGGIERO, ROBERT E. NAPPI, and IRVIN E. BRANCH, Administrative Patent Judges. BRANCH, Administrative Patent Judge. DECISION ON APPEAL Appeal 2011-000279 Application 11/509,178 2 STATEMENT OF CASE Appellant appeals under 35 U.S.C. § 134(a) from a rejection of claims 1, 2, 5, 6, 8, 9, 13-15, and 18-21. We have jurisdiction under 35 U.S.C. § 6(b). Claims 3, 4, 7, 10-12, 16, and 17 are cancelled. We reverse. Illustrative Claim The claims are directed to allocating cache lines in processing systems. Spec., Abstract. Claim 1, reproduced below, is illustrative of the claimed subject matter. Disputed limitations are italicized and annotated for reference infra. 1. A method comprising: configuring a cache to have a first cache line allocation policy for a memory address; receiving a first instruction associated with the memory address; receiving a second instruction subsequent to receiving the first instruction; [a] determining a second cache line allocation policy based on a number of accesses to the memory address that have occurred during an execution period prior to receiving the first instruction; [b] reconfiguring the cache to have the second cache line allocation policy in response to receiving the first instruction; and caching information associated with the second instruction at the cache in accordance with the second cache line allocation policy as set in response to receiving the first instruction. References The prior art relied upon by the Examiner in rejecting the claims on appeal is: Pickett US 5,958,045 Sep. 28, 1999 Appeal 2011-000279 Application 11/509,178 3 Adams, III Christie Moreno US 6,151,661 US 6,151,662 US 6,678,795 B1 Nov. 21, 2000 Nov. 21, 2000 Jan. 13, 2004 Rejections Claims 1, 2, 5, 8, 13, 14, 18, 19, and 21 stand rejected under 35 U.S.C § 103(a) as being unpatentable over Pickett and Moreno. Ans. 4-7. Claims 6 and 20 stand rejected under 35 U.S.C § 103(a) as being unpatentable over Pickett, Moreno, and Adams, III. Ans. 8. Claims 9 and 15 stand rejected under 35 U.S.C § 103(a) as being unpatentable over Pickett, Moreno, and Christie. Ans. 8-10. ANALYSIS We have reviewed the Examiner’s rejections in light of Appellant’s arguments in both the Appeal Brief and Reply Brief. We refer to the Briefs and the Answer for the respective positions of Appellant and the Examiner. 35 U.S.C. § 103 Rejection of Claims 1, 2, 6, 9, 13, and 20 Appellant’s contentions (App. Br. 6-11; Reply Br. 2-4) raise the issue of whether the Examiner erred in rejecting claim 1 under 35 U.S.C. § 103(a), finding that Pickett and Moreno collectively teach or suggest limitations [a] and [b]. In Pickett, a “start of access instruction” changes a microprocessor from a “global access mode” to a “local access mode,” which determines how memory operands are fetched into a cache for particular code sequences (e.g., loops). Pickett, col. 4, l. 57:col. 5, l. 8. The Examiner finds that Pickett teaches the limitations of claim 1, except that “Pickett does not expressly disclose the claim’s number of accesses,” recited in limitation [a]. Appeal 2011-000279 Application 11/509,178 4 Ans. 4, citing Pickett, Fig. 1; col. 4, l. 55:col. 5, l. 27; col. 5, ll. 35-42; and col. 5, l. 55:Col. 6, l. 13. The Examiner cites Moreno for limitation [a]. Ans. 4-5, citing Moreno, col. 8, ll. 40-67. Moreno teaches a saturating counter/decrementer to track an “access value” indicative of usage of prefetch cache lines. Moreno, col. 8, ll. 58-68. Appellant argues that the Examiner has erred by disregarding the “difference between cache line allocation based on accesses to a particular address . . . and express cache line allocation policy as disclosed by Pickett.” App. Br. 7. Appellant also argues that the Examiner has “confus[ed] prefetching with cache line allocation policy.” Id. at 8. Appellant alleges that adaptation of Moreno “could only have been accomplished by using hindsight” (id. at 10) further noting that Moreno’s counter measures an absolute number, whereas the independent claims “require the determination of a number of accesses over an execution period” (id. at 11). The Examiner finds that “Moreno’s teaching of prefetching is the cache line allocation policy.” Ans. 18. The Examiner further finds that the claimed execution period can be “any arbitrary sequence of instructions executing before the first instruction.” Id. at 20. We are persuaded by Appellant’s argument that prefetching and cache line allocation policy are not the same. See, App. Br. 8-9; Reply Br. 3. Moreno defines prefetching as requesting data or instructions in anticipation of future need (Moreno, Col. 4, ll. 58-61), whereas cache line allocation policy refers to the management of memory regions retaining data previously accessed (Spec., ¶ 16). We are also persuaded that the Examiner erred with respect to the determination of the length of the execution period Appeal 2011-000279 Application 11/509,178 5 being “arbitrary” (Ans. 20), when Appellant’s Specification makes clear that the number of clock cycles or instructions defining the execution period is specific, or “predetermined” (see, e.g., Spec. ¶¶ 23, 37). Accordingly, for the reasons stated by Appellant, the Examiner erred in rejecting claim 1 and commensurately claimed 13, the only pending independent claims. We therefore reverse the rejection of claims 1, 2, 5, 6, 8, 9, 13-15, and 18-21. CONCLUSIONS The Examiner erred in rejecting claims 1, 2, 5, 8, 13, 14, 18, 19, and 21 under 35 U.S.C § 103(a) as unpatentable over Pickett and Moreno. The Examiner erred in rejecting claims 6 and 20 under 35 U.S.C § 103(a) as unpatentable over Pickett, Moreno, and Adams, III. The Examiner erred rejecting claims 9 and 15 under 35 U.S.C § 103(a) as unpatentable over Pickett, Moreno, and Christie. DECISION For the above reasons, the Examiner’s rejection of claims 1, 2, 5, 6, 8, 9, 13-15, and 18-21 is reversed. REVERSED ELD