Ex Parte Zohar et al

Patent Trial and Appeal Board

Sep 3, 2014

11525420 (P.T.A.B. Sep. 3, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/525,420 09/22/2006 Ronen Zohar ITL.1426US (P24841) 1554
21906 7590 09/03/2014
TROP, PRUNER & HU, P.C.
1616 S. VOSS ROAD, SUITE 750
HOUSTON, TX 77057-2631
EXAMINER
CALDWELL, ANDREW T
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
09/03/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________________

Ex parte RONEN ZOHAR and SHANE STORY
____________________

Appeal 2012-003411
Application 11/525,420
Technology Center 2100
____________________

Before ELENI MANTIS MERCADER, JOHN G. NEW, and
JOHN F. HORVATH, Administrative Patent Judges.

HORVATH, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
Appellants file this under 35 U.S.C. § 134(a) from a final rejection of
claims 1–8, 10–12, 14–16, 18, 20, 22, 24–26, 28–31, 37 and 38. We have
jurisdiction under 35 U.S.C. § 6(b).
We affirm.

SUMMARY OF THE INVENTION
Appellants’ claimed invention is directed to rounding a floating point
number responsive to a received rounding instruction having an immediate
value that has separate fields for an override indicator and a rounding mode
(see Abstract). Claim 1, reproduced below, is illustrative of the claimed
subject matter:
1. A method comprising:
receiving a user-level rounding instruction of an
instruction set architecture (ISA) having a format including a
source operand, a destination operand and an immediate value,
in a control selector unit of a processor;
determining if a rounding mode override indicator of the
immediate value is active by decoding the immediate value in
the control selector unit;
if so, obtaining a rounding mode field of the immediate
value, the rounding mode field separate from the override
indicator, and dispatching the source operand and information
to control a rounding mode to a floating point unit of the
processor coupled to the control selector unit; and
executing a rounding operation on a source operand in
the floating point unit of the processor responsive to the user-
level rounding instruction and according to the information.

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REFERENCES AND REJECTIONS
1. The Examiner rejected claims 1–8, 10–12, 14–16, 18, 20, 22, 24–26, 28–
31, 37 and 38 under 35 U.S.C. § 112 ¶ 1 for failing to comply with both
the Written Description and Enablement Requirements.

2. The Examiner rejected claims 1–5, 7, 8, 10, 11 and 14–16 under 35
U.S.C. § 103(a) as unpatentable over Boggs1 in view of Smith2 and
further in view of Tanenbaum.3

3. The Examiner rejected claims 25, 26, 28–31, 37 and 38 under 35 U.S.C.
§ 103(a) as unpatentable over Boggs in view of Smith and further in view
of Tanenbaum.

4. The Examiner rejected claims 6, 12, 18, 20, 22 and 24 under 35 U.S.C. §
103(a) as unpatentable over Boggs in view of Smith and further in view
of Hansen.4

ISSUES
Whether the Examiner has erred in finding that:
A. Appellants have failed to provide sufficient written description in
the Specification to support the claims;

B. Appellants have failed to enable the inventions recited in the
claims to a person of ordinary skill in the art;

C. Boggs, Smith and Tanenbaum, in combination, teach a user-level
rounding instruction having an immediate value that includes
separate rounding mode indicator and rounding mode fields as
required by claim 1;

1 US Patent Pub. No. 20060095714 A1 published May 4, 2006
2 US Patent No. 5,696,709 issued Dec. 9, 1997
3 Andrew S. Tanenbaum, Structured Computer Organization 11 (2nd ed.
1984)
4 US Patent No. 5,812,439 issued Sept. 22, 1998
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D. Boggs, Smith and Tanenbaum, in combination, teach adding
different values to the operand of a rounding instruction based on
the operand’s relation to a threshold as required by claim 25;

E. Boggs, Smith and Hansen, in combination, teach a rounding
instruction having an immediate value that includes a precision
exception indicator field as required by claim 6; and

F. Boggs, Smith and Hansen, in combination, teach a status register
that stores a default round mode and status information indicating a
precision exception.

ANALYSIS
A. Whether Appellants have failed to provide sufficient written
description in the Specification to support the claims.

Appellants argue that the claims are adequately supported by the
Written Description, and that the Examiner has failed to identify any aspect
of any of the claims that is not so supported (App. Br. 18). The Examiner
finds the claims lack Written Description because they recite subject matter
that was not described in the Specification in such a way as to reasonably
convey to a person of skill in the art at the time of Appellants invention that
Appellants had possession of their invention (Ans. 25).
We agree with Appellants. Although the Examiner has stated the
well-known test to determine whether claims satisfy the Written Description
requirement, see Vas-Cath Inc. v. Mahurkar, 935 F.2d 1555, 1563 (Fed. Cir.
1991), the Examiner has not identified a single limitation alleged to be
lacking Written Description support, nor provided any explanation or
analysis tending to show that Appellants were not in possession of their
invention at the time their application was filed. In the absence of such
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evidence, we find the Examiner has failed to establish a prima facie case that
the claims are invalid under 35 U.S.C. § 112 ¶ 1 for lack of Written
Description, and reverse the Examiner’s rejection of the claims on this basis.

B. Whether Appellants have failed to enable the inventions recited in the
claims to a person of ordinary skill in the art.

Appellants argue that all pending claims are enabled since the
Specification discloses and describes multiple block diagrams and flow
charts illustrating the operations performed and the hardware involved at a
level of detail sufficient to allow a person of ordinary skill in the art to make
and use the invention without undue experimentation (App. Br. 16, 17).
The Examiner finds the claims lack enablement because Appellants have
maintained that the cited prior art, which the Examiner finds provides the
same level of detail as the Specification, is insufficient to render Appellants
invention obvious (Ans. 25–27).
We agree with Appellants. To reject a claim for lack of enablement,
the Examiner “bears an initial burden of setting forth a reasonable
explanation as to why [he] believes that the scope of protection provided by
that claim is not adequately enabled by the description of the invention
provided in the specification of the application.” In re Wright, 999 F.2d
1557, 1561-62, 27 USPQ2d 1510, 1513 (Fed. Cir. 1993). The Examiner has
not met that burden here.
In the absence of sufficient evidence, we find the Examiner has failed
to establish a prima facie case that the claims are invalid under 35 U.S.C. §
1112 ¶ 1 for lack of enablement, and we reverse the Examiner’s rejection of
the claims on this basis.
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C. Whether Boggs, Smith and Tanenbaum, in combination, teach a user-
level rounding instruction having an immediate value that includes a
separate rounding mode indicator and rounding mode fields.

Appellants contend that the combination of Boggs, Smith and
Tanenbaum does not teach “a user-level rounding instruction of an
instruction set architecture and an immediate value,” or making a
“determination . . . whether a rounding mode indicator of [the] immediate
value is active, and if so executing the rounding operation according to a
rounding mode field of the immediate value” (App. Br. 11–13). Appellants
proffer several arguments in support of their contention.
First, Appellants argue that the combination of Boggs, Smith and
Tanenbaum teaches away from receiving a user-level rounding instruction
because Boggs teaches a complex clipping instruction that includes a
rounding instruction (App. Br. 11–14). We are not persuaded by
Appellants’ argument.
The Examiner finds, and we agree, that through a judicious choice of
operands, Boggs’ complex clipping instruction can be reduced to a user-
level rounding instruction (Ans. 9–11). Moreover, the Examiner finds that
Boggs directly discloses a prior art user-level rounding instruction having an
immediate value that identifies one of a plurality of rounding modes (Ans.
12). Appellants argue that Boggs teaches away from using this user-level
rounding instruction by teaching its combination with other prior art, user-
level instructions in the formation of the complex clipping instruction (App.
Br. 13, 14). But the simple fact that Boggs’ invention lies elsewhere does
not teach away from using the disclosed prior art user-level rounding
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instruction. “The use of patents as references is not limited to what the
patentees describe as their inventions or to the problems with which they are
concerned. They are part of the literature of the art, relevant for all they
contain.” In re Heck, 669 F.2d 1331, 1332–33 (Fed. Cir. 1983).
Next, Appellants argue that the combination of Boggs, Smith and
Tanenbaum fails to teach or suggest a rounding instruction whose immediate
value includes separate fields for an override indicator and a rounding mode
identifier (App. Br. 11–13). We are not persuaded by Appellants’ argument.
The Examiner finds, and we agree, that Smith discloses these
limitations to a person of ordinary skill in the art (Ans. 14). In particular, the
Examiner finds that Smith’s LOAD FP INTEGER instruction discloses an
immediate value that includes an M3 field that encodes both an override
indicator and a rounding mode identifier, and that it would have been within
the level of skill in the art at the time of the invention to encode Smith’s
override indicator and rounding mode identifier in different fields of the
immediate value rather in the same M3 field (Id. at 14–17).
Smith discloses a computer system whose default floating point
rounding mode may be overridden by a rounding mode designated by an
instruction (Smith, Abs.). Smith also discloses a LOAD FP INTEGER
instruction that includes an immediate value having an M3 field that controls
how floating point numbers are rounded (Id. at 3:44–46). When all three
bits of the M3 field are zero, floating point numbers are rounded according
to a default rounding mode stored in a status register (Id. at 3:57, 58).
However, when one or more bits of the M3 field are non-zero, floating point
numbers are rounded according to the rounding mode identified by the M3
field bits (Id. at 3:58–60).
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Consequently, we agree with the Examiner’s finding that Smith’s M3
field encodes both an override indicator and a rounding mode identifier.
Moreover, we agree with the Examiner’s finding that a person of ordinary
skill in the art at the time of Appellants’ invention would have known that
Smith’s override indicator and rounding mode identifier could have been
encoded in the same or different fields of the immediate value. As the
Examiner explained, encoding the information in the same fields would
conserve instruction bits, while encoding the information in different fields
would simplify decoding logic (Ans. 17). Indeed, Hansen teaches that exact
concept, albeit in terms of exception handling indicators and rounding mode
identifiers, namely, that exception handling indicators and rounding mode
identifiers can be encoded together using 3 bits rather than separately using
7 bits in order to conserve operation code space (See Ans. 32–34; Hansen,
4:16–40).
In view of the foregoing, we agree with the Examiner’s finding that
the combination of Boggs, Smith and Tanenbaum teaches “receiving a user-
level rounding instruction of an instruction set architecture and an immediate
value” and making a “determination . . . whether a rounding mode indicator
of [the] immediate value is active, and if so executing the rounding operation
according to a rounding mode field of the immediate value” as required by
claim 1 (App. Br. 11–13). Accordingly, we affirm the Examiner’s rejection
of claim 1, and for the same reasons the Examiner’s rejections of claims 2–5,
7, 8, 10, 11 and 14–16.5

5 Appellants do not separately argue for the patentability of claims 2–5, 7, 8,
10, 11 and 14–16. We therefore consider the patentability of these claims
based on the patentability of claim 1. (37 C.F.R. § 41.37(c)(1)(iv))
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D. Whether Boggs, Smith and Tanenbaum, in combination, teach adding
different values to the operand of a rounding instruction based on the
operand’s relation to a threshold.

Appellants proffer three arguments for the patentability of claim 25
over the combination of Boggs, Smith and Tanenbaum. Appellants first
argue that the combination fails to disclose a user-level round instruction
having an override indicator in an immediate value (App. Br. 14). We
discussed this contention above, in reference to claim 1, and are not
persuaded by Appellants argument for the reasons noted supra.
Appellants next argue that claim 25 is patentable over the combination
of Boggs, Smith and Tanenbaum, because the combination fails to teach or
suggest adding different values to the operand of a rounding instruction
based on the operand’s relation to a threshold (App. Br. 14).
We note that the Examiner did not find that the Boggs, Smith, and
Tanenbaum combination disclosed this limitation. Instead, the Examiner
took Official Notice that the round-half up procedure was well known to
persons of skill in the art at the time of Appellants’ invention, and disclosed
the limitation (Ans. 20, 22). The Examiner described the round-half-up
procedure as rounding positive numbers (i.e., numbers greater than a
threshold of zero) by adding +0.5 to them and truncating, and rounding
negative numbers (i.e., numbers less than the threshold of zero) by adding
-0.5 to them and truncating (Id.). We agree with the Examiner’s finding.
The Examiner is entitled to take Official Notice of “facts beyond the
record which, while not generally notorious, are capable of such instant and
unquestionable demonstration as to defy dispute.” In re Ahlert, 424 F.2d
1088, 1091 (CCPA 1970). Here, the Examiner has not only identified the
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round-half-up procedure, but has provided an instant and unquestionable
explanation of it that defies dispute. Moreover, Appellants have neither
traversed the Examiner’s identification of round-half-up as a well-known
prior art rounding procedure, nor disputed the Examiner’s explanation of it.
Consequently, we adopt and affirm the Examiner’s finding that the round-
half-up procedure was well known to persons of skill in the art at the time of
Appellant’s invention, and teaches adding different values to the operand of
a rounding instruction based on the operand’s relation to a threshold. See In
re Chevenard, 139 F.2d 711, 713 (CCPA 1943).
Appellants third and final argument for the patentability of claim 25
over the combination of Boggs, Smith, and Tanenbaum is the combination
fails to teach or suggest an instruction set architecture (ISA) having multiple
round instructions to round operands having different data types. To
advance this argument, Appellants have traversed the Examiner’s Official
Notice that ISA’s having separate instructions for single and double
precision data types were well known to persons of skill in the art at the time
of Appellants’ invention on the grounds that the Official Notice was raised
for the first time on Final Rejection and failed to instantly and
unquestionably demonstrate that such instructions were well known (App.
Br. 14, 15).
To successfully traverse an Officially Noticed finding of fact,
Appellants must do more than simply object to the timing of the Official
Notice or restate the test under which it is proper for the Examiner to take
Official Notice. In particular, Appellants must “specifically point out the
supposed errors in the examiner’s action, which would include stating why
the noticed fact is not considered to be common knowledge or well-known
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in the art.” MPEP § 2144.03(c); see also, Chevenard at 713. Appellants
have failed to do so here. As to the timing, although it is true that the
Examiner first took Official Notice in the Final Office Action, it is also true
that Appellants had adequate opportunity to point out any supposed errors in
the Examiner’s action or why the noticed fact was not common knowledge
in their Appeal Brief. As the Examiner correctly noted:
Applicants could have provided a technical reference which
called into question the examiner’s Official Notice, and the
examiner would have supplied one or more references
supporting it. Applicants could also have stated on the record
they were unaware of any prior art supporting the examiner’s
Official Notice, and the examiner would have supplied one or
more references supporting it.
(Ans. 23, 24). Because Appellants have failed to meet their burden to
traverse the Examiner’s finding that ISA’s having different instructions for
different data types were well known to persons of skill in the art at the time
of Appellants invention, we affirm, adopt the Examiner’s finding as our
own, and enter the fact into evidence.
In view of the foregoing, we find that the combination of Boggs,
Smith and Tanenbaum teaches adding different values to the operand of a
rounding instruction based on the operand’s relation to a threshold, and that
the rounding instruction is one of multiple rounding instructions in the
instruction set of an instruction set architecture, where each rounding
instruction performs round operations on operands having different data
element types as required by claim 25. Thus, we affirm the Examiner’s
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rejection of claim 25, and for the same reasons the Examiner’s rejections of
claims 26, 28–31, 37 and 38.6

E. Whether Boggs, Smith and Hansen, in combination, teach a rounding
instruction having an immediate value that includes a precision
exception indicator field.

As a preliminary matter, Appellants argue that the rejection of claim 6
was improper because it was not based upon Tanenbaum, which was used to
reject claim 1 from which claim 6 depends (App. Br. 15). The Examiner
finds that since Tanenbaum was not relied upon to reject a specific limitation
of claim 1, but merely to establish knowledge common to a person of
ordinary skill in the art at the time of Appellants invention, it was not needed
to reject claim 1 and is therefore not needed to reject claim 6 (Ans. 29–30).
At the outset, we treat the Examiner’s omission of Tanenbaum in the
rejection of dependent claim 6 as inadvertent error, since it is necessarily
incorporated by reference given the dependence of claim 6 from claim 1.
Moreover, in rejecting claim 1, the Examiner found that Boggs directly
disclosed a prior art, user-level, rounding instruction as well as a complex
clipping instruction that included the rounding instruction (Ans. 9, 12; see,
also Boggs, ¶¶ 29, 30). Since the Examiner cited Tanenbaum simply to
support his proposition that a person of skill in the art at the time of
Appellants invention would have known that Boggs’ rounding instruction
could have been used as a stand-alone instruction or incorporated into the
more complex clipping instruction, and since Boggs is prior art for all it

6 Appellants do not separately argue for the patentability of claims 26, 28–
31, 37 and 38. We therefore consider the patentability of these claims based
on the patentability of claim 25. (37 C.F.R. § 41.37(c)(1)(iv))
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discloses, In re Heck, 669 F.2d at 1332–33, we find that Tanenbaum was at
best cumulative evidence used in the rejection of claim 1, and its omission in
the rejection of claim 6 was harmless error.
Appellants next argue that the combination of Boggs, Smith and
Hansen fails to teach or suggest a rounding instruction with an immediate
value that includes a precision exception indicator (App. Br. 15). As
disclosed in Appellants’ Specification, a precision suppression indicator
(claim 6) or precision override indicator (Figure 3) is a bit that “may be set
to indicate allowance of inexact results such that no precision exception,
even if occurring during operation of the associated instruction, will cause
setting of an exception flag within a status register” (Spec. ¶ 23, Fig. 3). In
other words, a precision exception indicator is a flag that can be set in a field
of the immediate value of an instruction that indicates whether an exception
flag should be set in a status register when the result of the instruction is
inexact. The Examiner finds, and we agree, that Hansen teaches a floating
point instruction having an immediate value field that includes an inexact /
precision exception indicator (Ans. 25).
Hansen discloses a method for “encoding floating point information
within processor instructions” (Hansen, 1:6–9). ”The floating point
information indicates whether an exception trap should occur and the type of
rounding to be performed upon ‘inexact’ arithmetic results” (Hansen, Abs.).
Hansen discloses that “[t]here are generally five different exception types
which may occur in processors of prior art systems,” including an ‘X’ or
inexact exception type indicating an inexact result that needs to be rounded
(Id. at 1:41–58). Hansen discloses an embodiment of his invention that
incorporates three bits of control information in a floating point instruction
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to allow the selection of an arbitrary rounding mode “with all exception
traps excluding inexact (X) enabled,” and the selection of no rounding mode
with “all exception traps, including inexact (X) enabled” (Id. at 4:34–40)
(emphasis added). Hanson also discloses a simpler embodiment that uses
“five bits of control for each exception type (V, Z, U, O, and X), and two
bits to select rounding (N, T, C, F)” (Id. at 4:16–20). In other words,
Hansen discloses using a single bit in an immediate value of a floating point
instruction to indicate whether an inexact exception flag ‘X’ should or
should not be set or enabled.
Accordingly, we affirm the Examiner’s rejections of claims 6 and 12.7

F. Whether Boggs, Smith and Hansen, in combination, teach a status
register that stores a default round mode and status information
indicating a precision exception.

Appellants first argue that claim 18 is patentable because the
combination of Boggs, Smith and Hansen fails to disclose a user-level round
instruction having an immediate value with separate fields for an override
indicator and round mode identifier, where the round mode identifier
encodes multiple round modes (App. Br. 16). We addressed this argument
above, in reference to claim 1, and found Appellants argument unpersuasive
for the reasons noted supra.
Appellants next argue that claim 18 is patentable because the Boggs,
Smith and Hansen combination fails to disclose a user-level round
instruction that includes an immediate value or control field that includes a

7 Appellants do not separately argue for the patentability of claim 12. We
therefore consider the patentability of claim 12 based on claim 6. (37 C.F.R.
§ 41.37(c)(1)(iv))
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precision exception indicator (App. Br. 16). We likewise addressed this
argument above, in reference to claim 6, and found Appellants argument
unpersuasive for the reasons noted there.
Finally, Appellants argue that claim 18 is patentable because the
Boggs, Smith and Hansen combination fails to disclose a register that stores
a default round mode and status information indicating a precision exception
(App. Br. 16). The Examiner finds, and we agree, that both Smith and
Hansen disclose these limitations (Ans. 31).
As noted above, Hansen discloses a system and method for encoding
floating point information within processor instructions (Hansen, 1:6–9).
Hansen discloses that CPUs generally use status registers to store mode bits
and status information, including bits indicating whether certain interrupt
flags have been set by the processor (Id. at 1:13–18). Hansen further
discloses that CPUs can set inexact or precision exception flags in their
status registers to alert users to the fact that inexact results have been or need
to be rounded (Id. at 1:30–39).
Hansen’s floating point instruction includes rounding mode bits 3–5,
and type bits 26 and 27 (Hansen, Fig. 5). When type bit 27 is null or zero,
the CPU sets exception flags and performs rounding according to a default
rounding mode (Id. at 8:63–65). By contrast, when type bits 26 and 27 are
set, the CPU sets exception flags and performs rounding according to the
rounding and exception modes encoded in bits 3–5 (Id. at 8:65–68). As
shown in Tables 8 and 9, when bits 3–5 take on values between 0 (000) and
4 (100), inclusive, Hansen does not set the inexact exception flag (X=0). By
contrast, when bits 3–5 take on the value of 5 (101), Hansen does set the
inexact exception flag (X=1) (Id. at 9:1–45).
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Similarly, Smith discloses:
A computer system having a default floating point rounding
mode that may be overridden by a rounding mode designated
by an instruction. The current machine rounding mode is stored
in a register, and an instruction includes a field for specifying
whether rounding should be performed according to the current
rounding mode or according to another rounding mode during
execution thereof.
(Smith, Abs.) Figure 4 of Smith illustrates a “floating-point-control (FPC)
register 210 . . . [that] contains the mode (i.e., rounding mode), mask, flag
and code bits” (Id. 2:54–57). As the Examiner correctly found, bits 6 and 7
in byte 3 of FPC register 210 stores a default round mode, while bit 4 in byte
1 of FPC register 210 stores a status flag indicating whether a precision or
inexact exception has occurred (Id., Fig. 4).
In view of the foregoing, we find that the combination of Boggs,
Smith and Hansen teaches a system that receives and executes a user-level
round instruction having an immediate value with separate fields for an
override indicator and round mode identifier, where the round mode
identifier encodes multiple round modes, and where the system includes a
status register that stores a default round mode and status information
indicative of a precision exception as required by claim 18. Thus, we affirm
the Examiner’s rejection of claim 18, and for the same reasons the
Examiner’s rejections of claims 20, 22, and 24.8

8 Appellants do not separately argue for the patentability of claims 18, 20, 22
and 24. We therefore consider the patentability of the claims based on the
patentability of claim 18. (37 C.F.R. § 41.37(c)(1)(iv))
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CONCLUSIONS
The Examiner erred in finding that:
A. Appellants failed to provide sufficient written description in the
Specification to support the claims; and

B. Appellants failed to enable the inventions recited in the claims to a
person of ordinary skill in the art.

The Examiner did not err in finding that:
C. Boggs, Smith and Tanenbaum, in combination, teach a user-level
rounding instruction having an immediate value that includes separate
rounding mode indicator and rounding mode fields as required by
claim 1;

D. Boggs, Smith and Tanenbaum, in combination, teach adding different
values to the operand of a rounding instruction based on the operand’s
relation to a threshold as required by claim 25;

E. Boggs, Smith and Hansen, in combination, teach a rounding
instruction having an immediate value that includes a precision
exception indicator field as required by claim 6; and

F. Boggs, Smith and Hansen, in combination, teach a status register that
stores a default round mode and status information indicating a
precision exception.

DECISION
The Examiner’s decision rejecting claims 1–8, 10–12, 14–16, 18, 20,
22, 24–26, 28–31, 37 and 38 under 35 U.S.C. § 112 ¶ 1 is reversed.
The Examiner’s decision rejecting claims 1–8, 10–12, 14–16, 18, 20,
22, 24–26, 28–31, 37, and 38 under 35 U.S.C. § 103(a) is affirmed.

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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2009).

AFFIRMED

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